Parameterizable Synthesizable Code (was [oc] Help::)

[Jason Silcox <jsilcox@yahoo.com>]

--- Dharmeshbhai PATEL <dpatel@ifrance.com> wrote:
> I want to do this operation in VHDL
> 
>   N = 2**Ns.
> 
> Where Ns is programable...
> 
> How can i write a synthetizable vhdl code.

architecture ...

  signal n : signal_type;

begin

  n <= (signal_type'left -1 downto Ns +1 => '0') &
       '1' & (Ns -1 downto 0 => '0');

end architecture ...

Assuming signal_type has enough width to support the
resolution you need.  Also, signal_type has to be defined
as a (max -1 downto 0) array and not (0 to max -1) array...

This concept can be used also to take static objects
(i.e. generics, constants & immediates) and assign signal bit
widths and initial values using most of the std_logic_arith
functions.  I have yet to verify that these are actually
processed correctly by all synthesis tools, but if not I
would push to have this kinda of feature added...

A few examples of this are:

- Setting the bit_width of a memory address dependent on the
  maximum amount of memory that is needed. Expecially were the
  amount of memory varies and isn't linear...

- Setting a constant that is calculated using functions such
  as Log, Cosine, Sine, etc...
  
- Filling Look-Up Tables with calculated values which have a
  parameterized precision... (Very useful in DSP implementations)

I've come up with some examples of these type of assignments.
While designing an very complex interleaver/deinterleaver with
an external RAM controller, these came in handy for dynamically
setting the hardware requirements by supplying the actual size
of the interleaver/deinterleaver data... In the next version of
this system all that will be necessary is to change the maximum
size constant and everything will scale to meet the need...

For all the software people out there, this is taking advantage
of the "pre-processing" that occurs during synthesis... Once the
real synthesis step occurs, all the non-synthesizable functions
should have been evaluated to "static" objects and thus shouldn't
cause any errors...

Is this helpful for people... Since most of the cores are in
verilog, is it really useful to talk about things that can only
be done in VHDL (at least right now)...

Thanks for listening,
---
Jason Silcox

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