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[oc] CAN error question



Hi, guys.

 

I have a question regarding CAN error counter.

 

 

 

CAN specifications 2.0 says for the error active flag:

 

The ACTIVE ERROR FLAG consists of six consecutive 'dominant' bits.

 

An ’error active’ station detecting an error condition signals this by transmission of an

ACTIVE ERROR FLAG. The ERROR FLAG’s form violates the law of bit stuffing (see

CODING) applied to all fields from START OF FRAME to CRC DELIMITER or destroys

the fixed form ACK FIELD or END OF FRAME field. As a consequence, all other

stations detect an error condition and on their part start transmission of an ERROR

FLAG. So the sequence of ’dominant’ bits which actually can be monitored on the bus

results from a superposition of different ERROR FLAGs transmitted by individual

stations. The total length of this sequence varies between a minimum of six and a

maximum of twelve bits.

 

 

Further it says for error delimiter:

 

The ERROR DELIMITER consists of eight 'recessive' bits.

After transmission of an ERROR FLAG each station sends 'recessive' bits and

monitors the bus until it detects a 'recessive' bit. Afterwards it starts transmitting seven

more 'recessive' bits.

 

 

Now my question is regarding receive error counters. It says in the spec:

When a RECEIVER detects a 'dominant' bit as the first bit after sending an ERROR

FLAG the RECEIVE ERROR COUNT will be increased by 8.

 

What is now "the first bit after sending an ERROR FLAG" ?

Is it the 7th bit? The spec says that the error flag can be 6-12 bit long. Is it the 13th bit?

or 1st bit after the error delimiter?

 

 

Thanks for the help.

 

Best regards,

  Igor