Re: [oc] Synthesizable Testbench

[John Sheahan <jrsheahan@optushome.com.au>]

On Sun, Feb 02, 2003 at 04:59:32PM -0000, tanveer  tan wrote:
> can i get more links or suggetsted books on  synthesizable 
> testbench
> 
> 
> wht i get from the discusion so far is tht the synthesizable 
> testbench is a fsm that reads the test data form the ram and pass 
> tht to the test module and the recive the result from the module 
> after some dely depending on the module and store tht in the ram 


this is possible, but not required. Whats in your test bench?
Its can also calculate the answer, rather than look up.
And it can react to signals from the model. lookup OR algorithmic.
Any style you put in the synthesized code - can also go in the TB.

Its up to the designer's imagination.  and the TB does not have to be
100% anything.  Just needs to simulate fast.

> ,
> 
> if so then how would it be possible to use a single clock to read 
> the test data from the ram and store the result in to the ram?

who said there was one ram? or if so, that it has a single port?

john


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