Re: [oc] Synthesizable Testbench

["tanveer tan" <tanveer008@rediffmail.com>]

can i get more links or suggetsted books on  synthesizable 
testbench


wht i get from the discusion so far is tht the synthesizable 
testbench is a fsm that reads the test data form the ram and pass 
tht to the test module and the recive the result from the module 
after some dely depending on the module and store tht in the ram 
,

  is tht it?
if so then how would it be possible to use a single clock to read 
the test data from the ram and store the result in to the ram?

tanveer

On Sun, 26 Jan 2003 Ho, Wen Jei      x4297 wrote :
>When I worked for IBM 9 years ago, there was a hardware 
>simulator,
>
>code name "EVE", took net-list only. I had to clone i960/VHDL 
>to
>
>get net-list to use EVE. The entire testbench was 
>Synthesizable.
>
>
>
>There is a book talking about "Synthesizable Testbench":
>
>Page 20, session 2.2.5, "Principles of Verifiable RTL Design",
>
>Year 2000 by Lionel Benning and Harry Foster.
>
>
>
>Wen
>


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