Re: [oc] Design Question

[Richard Herveille <richard@asics.ws>]

> Hi Gents,
>
> I am planing to work with some IP cores for an application. I have found
> an IP core that I need. Before starting implementation I would like to ask
> you some basic questions..:
>
> * The IP core I found is in Verilog but I am going to use vhdl language
> for my design files. Does it matter whether IP core is in verilog and rest
> of my application files are in VHDL?. Is there any design constrains,
> pros. and cons. regarding this issue?

Not really, most synthesis tools can handle mixed-language designs. There 
might be a few minor issues. For example Verilog allows a signal name to end 
with a '_', VHDL pukes on this. However these issues should be simple to 
resolve.

>
> * I have a Spartan II dev. board from Digilent. For final application I
> need to have a PCB. In order to realize this, do I just need a Spartan
> chip and a programmed SPROM?

Basically yes.
That is, you need a multi-output power supply - modern FPGAs require separate 
Vcore and Vio supplies (might be the same voltage though) - and some 
connections to the outside world of course.

> And is there anyone who soldered a
> PQ208 package? :-)

Yep did it. It requires a steady hand and some patience, but it is certainly 
doable.

Richard

>
>
> Cheers,
>
> Aris

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