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Re: [oc] about instance components

To: cores@opencores.org
Subject: Re: [oc] about instance components
From: John Sheahan <jrsheahan@optushome.com.au>
Date: Tue, 19 Nov 2002 19:55:11 +1100
In-Reply-To: <OF447C1725.B1874DD5-ON48256C76.0010BBBA@diamond.philips.com>
References: <OF447C1725.B1874DD5-ON48256C76.0010BBBA@diamond.philips.com>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org
User-Agent: Mutt/1.3.25i

On Mon, Nov 18, 2002 at 07:08:44PM -0800, haoguang.guo@philips.com wrote:
> hi,
>    i am a newbie for verilog hdl. I have a problem to instance N times of same components in xilinx ise4.1.
> Here N is a paremeter.It seems the verilog does not support GENERATE like VHDL.
>   please help me !
> thank you
> 
newer verilogs (2001 standard compliant at least) support the 
generate statement

what verilog simulator/synthesis are you using?

John
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References:
- [oc] about instance components
  - From: haoguang.guo@philips.com

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