Re: [oc] I2C slave model

[Richard Herveille <richard@asics.ws>]

>hi,
>i had developed a simple i2c bus master in VHDL and was using I2C
>slave verilog code taht was available over here for the purpose of
>testing. When i am giving the start, and the address of the slave, the
>slave is not generating the acknowledgement bit. Since i donot know
>verilog, i couldnot figureout why such problem came up.
>Shouldn't the slave send an acknowledgement bit after the master
>addresses it ?

Yes it should.

>  If yes, can anybody let me know it the verilog slave
>code available over here would respond with the acknowledement bit or
>not ?

And yes it does. The testbench for the i2c_master_core tests this bit.

Richard


>Also let me know if there is slave module for simualtion in VHDL
>anywhere on the web.
>Thanking you all in advance
>regards,
>Vikas
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