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[oc] cores list is becoming full of crap



Sure, Paul,

Then take a board with a xilinx xc9536 on it and implement the whole design.
If you want a real chalange, then implement an ethernet PHY in it also.
Should be finished not later than in Monday if you're not a starter in
Verilog.
If you're a starter, consider using on of the WhateverToVerilog translators.

Come on, guys, this mailing list is becoming full of crap. It used to be a
good
list full of great ideas. The question at the beginning was simple: "What to
do
for a final project" and not "How to spend the rest of my life". I wouldn't
be
surprised if the guy that put the initial question already left.

Let's talk about "real" things and not just writing tons of mails "to make a
point".

Regards,
	Igor


>
> Marko,
>
> find a opencore for Ethernet, implement it and then use the
> TCPsocket implementation
> off a copy of Linux and translate the C into Verilog (or VHDL if
> you are brave).
> Not bad for 10seconds of thinking egh? Anything I missed?
>
> Paul
>
> > -----Original Message-----
> > From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> > Behalf Of Marko Mlinar
> > Sent: 20 December 2001 14:33
> > To: cores@opencores.org
> > Subject: Re: [oc] Re: How to create such signal wave using VHDL?
> >
> >
> > > for my 2pence worth, I know people have done a combined Ethernet and
> > TCP/IP stack in a
> > > single FPGA which I think is pretty cool. Although they did
> 'cheat' and
> > used a C to netlist
> > > compiler instead of Verilog but if you are up for a challenge
> I think its
> > a neat idea. Given
> > > the popularity of TCP/IP these days it would give you a nice
> boost when
> > they ask you at
> > > interviews "do you have any experience of TCP/IP?".
> > How much time you think one person would need to finish such project?
> >
> > Marko
> >
> >
> > --
> > To unsubscribe from cores mailing list please visit
> http://www.opencores.org/mailinglists.shtml
> >
> --
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>

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