RE: [oc] Re: How to create such signal wave using VHDL?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Sam,

interesting. It may be a better idea to expand Verilog to become more C like.
I'll look at it and see what can be done with it.

Paul

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Sam Gladstone
> Sent: 21 December 2001 23:03
> To: cores@opencores.org
> Subject: RE: [oc] Re: How to create such signal wave using VHDL?
> 
> 
> That is called a Verilog simulator written in C
> with a canned verilog program inside it.
> Honestly, you would have to write all of the
> event handling, 4 state logic rules, and the
> list goes on.
> It would be like building a verilog simulator
> to run a single Verilog program.
> 
> <Shameless Plug for GPL Icarus>
> A much easier way is to use Icarus verilog
> simulator. (Free as in GPL free.) It can
> write target code that joins with C and can run
> natively.  That would be your most
> productive avenue. Plus you would be involved
> in a truly worthwhile project.
> 
> I wrote the SXP processor in Verilog using
> Icarus and it runs great. I also simulated the
> processor in Verilog-XL to make sure that Icarus
> and Verilog-XL agreed on simulation.
> 
> It also can synthesize to Xilinx parts and several other
> targets.
> 
> Check it out at
> 
> www.icarus.com
> 
> Try to use the latest Dev release as it blows away the
> official 0.5 release.
> It is updated almost twice a month with big improvements.
> 
> Used with GTKWAVE, it really feels comfortable.
> 
> You can write code that is completely portable to your
> work related verilog projects.
> 
> </Shameless Icarus plug>
> 
> Regards,
>  Sam Gladstone
> 
> 
> 
> 
> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Paul McFeeters
> Sent: Friday, December 21, 2001 10:33 AM
> To: cores@opencores.org
> Subject: RE: [oc] Re: How to create such signal wave using VHDL?
> 
> 
> Verilog to C translator? Na it will never catch on! lol
> Too much eggnog?
> 
> > -----Original Message-----
> > From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> > Behalf Of Marko Mlinar
> > Sent: 21 December 2001 12:06
> > To: cores@opencores.org
> > Subject: Re: [oc] Re: How to create such signal wave using VHDL?
> >
> >
> > > Marko,
> > >
> > > find a opencore for Ethernet, implement it and then use the TCPsocket
> > implementation
> > > off a copy of Linux and translate the C into Verilog (or VHDL if you are
> > brave).
> > > Not bad for 10seconds of thinking egh? Anything I missed?
> >
> > Don't want to argue - but of course:
> > - first you have to use Igor's Ethernet, which shouldn't be a problem
> > - you have to make wishbone interface in VERILOG
> > - supposingly your C to Verilog tool works (if you have 10k$ to buy it)
> you
> > still
> > have to:
> > - obtain TCP/IP stack from e.g. Linux
> > - change the behaviour of TCP/IP from SW behaviour to more like HW one,
> > which is IMHO
> >   not an easy task and change programming interface. I suppose you don't
> > have malloc
> >   or files supported with translator.
> > - obtain (= buy) sythesis software
> > - meet timing constraints, maybe not so simple
> > - buy a couple of big FPGAs to fit the whole design, because the Verilog
> to
> > C translator yields
> >   big code...
> >
> > IMHO this is at least 2my of hard work...
> >
> > Marko
> >
> >
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