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RE: [oc] Handel-C replacement, name is done now for thecoding.
>Martin,
>
><snip bit about CPU+Linux Kernel on chip>
>
>> Sounds very ambitious - I'd start by flashing some lights :-) I have to
>say the Celoxica's
>> video demos are *very* impressive, generating VGA real-time from C
>impresses the pants off
>> most softies, so a demo board with a RAMDAC on would be nice...
>
>But I am ambitious, yes I have flashed lights (not in my C program yet just
>VHDL) but I like
>to dream of tomorrow and make it happen.
Ambitious is good! Always have a good goal to aim at :-)
<snip>
>A couple of resisters attached to an FPGA and I will have my own 12bit
>(hopefully soon 24bit)
>VGA interface according to the designs I've found. I was hoping to use the
>Block RAM SRAM units
>but at only 512bytes each my initial screens would be rather blocky shall
>we say? Monochrome I
>could do say 70 x 50 pixels off one but will use them for higher resolutions
>for now.
That's the neat bit about Celoxica's demos - they don;t use a frame buffer, they generate on the fly. Have you seen the raytracing demo. Real-time reflections from a complex object, 640x480x30fps, rendered a pixel at a time on the fly.
They could do with showing some demos on the site.
That
>reminds me Tony has a pre-made VGA connector for my boards so will look to
>order one or two of
>those for later.
>
Which board do you have?
>> They generate directly to EDIF normally, although they do have a VHDL
>output flow now. YOu
>> might get some info from some of the papers written about Handel-C when it
>was still an academic
>> thing.
>
>I did try to find some of them but Oxford (where the academic papers were
>written have removed them
>probably at the bequest of Mr. Page).
:-(
I did place call for XNF and EDIF
>information but I suspect
>going to Verilog would be so much easier than straight into EDIF/XNF for now
>(if not pls email me).
>I'm studying Verilog at the moment as VHDL (or maybe just Webpack) is giving
>me so much grief its
>unreal.
Then you'll be wanting Icarus verilog (http://www.icarus.com/eda/verilog/), I imagine. Synthesis as well as simulation IIRC. About time I learned Verilog also!
Even a simple 8 stage FSM I did, clocked at 1Hz doesn't work right
>with Webpack not to
>mention some of the freaky errors it likes to produce at perfectly legal
>things like using
>functions or procedures, I don't need extra headaches during development
>phases.
>
Ahhh, there's legal and there's synthesisable though... AFAIK (which isn't much) WebPack simulates by first synthesising.
<snip>
>> You never know... Of course, if you open the source, Celoxica can nick
>your ideas, even without nicking
>> the source-code can't they?
>
>The idea of opening the source will be for everybody to be able to use it
>(or nick it as you call it) but
>then how would Celoxica and others expect to charge so much for something
>thats 'public property'? Do you
>think that people would get away with charging $25,000 for a copy of the
>Linux Kernel?
No, but they do get away with charging reasonably huge amounts for proprietary Unix kernels, which may or may not have Linux ideas (not source) in them.
I will be a little while before I open the source even in
>ideal conditions alas. Apart from writing it I will have to check
>that any technique I use doesn't infringe on copyrights from my previous
>programming days, then I have to
>clean it up. Don't want everyday laughing at me do I? But my main point is
>$25,000 a year for any program
>is just taking the P*** out of us.
They do have a 'research' license now which is cheaper (I heard)
<snip>
>Handel-C is copyright of Mr. Page or Celoxica, whichever obviously we can't
>use it, another company does
>SystemC and I think theres also CycleC but I have an idea for a name (won't
>tempt name-claim-jumpers by
>mentioning it but its pretty good).
Can't wait :-)
Happy hacking!
Martin
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