Re: [oc] Audio synthesis core

["Damjan Lampret" <lampret@opencores.org>]

> Aha. I suppose I should have seen that one coming.
> Doesn't the Xilinx XC series have multipliers actually
> on board? Anyway, despite this I shall still be
> designing a new multiplier because I believe that it
> is always a big advantage to have worked out the
> design yourself, and the experience will be something
> that I can describe and share with anyone in OC.
>

Well for pipelined multiplier you can generate it yourself with CORE
Generator System (and I also think Xilinx LogiBLOX). But result might not be
independent and it might work only in specific  Xilinx FPGA. So this is good
if you want to support only a certain subset of FPGAs.

Better way is to use technology independent multiplier that can also be
synthesized for standard cell (ASIC).

Multiplier block in your design should be replaceable block so that user of
your core can use multiplier that is optimized for his technology
(generetaed by COREgen if he is using Xilinx FPGAs, DesignWare multiplier if
he is using Synopsys targetting ASICs etc).

regards,
Damjan


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