Re: [oc] Audio synthesis core

[Miggsy Fox <miggs_ectomorph@yahoo.com>]

--- Rudolf Usselmann <rudi@asics.ws> wrote:
> on 6/17/01 7:29, Miggsy Fox at
> miggs_ectomorph@yahoo.com wrote:
> 
> > Hi OC People
> > 
> > Just started writing the multiplier for my audio
> > synthesis OC project. Basically, it's a sort of
> > wave-table like synthesiser, but with some
> advanced
> > filtering and modulation synthesis. I figure that
> > perhaps the general purpose MAC core might
> actually
> > form a building block for the audio synth.
> However, I
> > might discover that there are some mods to the MAC
> > core that make it functionally rather different,
> > therefore I am starting with a new multiplier. I
> am
> > thinking of incorporating the accumulator into the
> > multiplier structure somehow to reduce prop
> delays. Do
> > have a quite efficient structure worked out for a
> > 4-bit version. That's obviously just a starting
> point!
> > Do people recommend that I start learning VHDL or
> > Verilog first? Have only really scratched the
> surface
> 
> I believe Verilog is easier to learn and get started
> with.
> 
OK thanks for that advice, I shall code it up in
Verilog then.

> > with these tools. I know that someone mentioned
> the
> > DesignWare multiplier in the Synopsys tools, can
> > anyone comment on the suitability of that
> multiplier,
> > bearing in mind that I only need a fixed-point
> > version?
> 
> I would not recommend using the DesignWare
> multipliers, as the
> DesignWare library is part of a very expensive
> synthesis tool
> and not everybody would have access to it.
> 
Aha. I suppose I should have seen that one coming.
Doesn't the Xilinx XC series have multipliers actually
on board? Anyway, despite this I shall still be
designing a new multiplier because I believe that it
is always a big advantage to have worked out the
design yourself, and the experience will be something
that I can describe and share with anyone in OC.

> > I will draw up a high level functional block
> diagram.
> > I am toying with the idea at the moment of working
> out
> > a direct interface to the RISC cores in OC. That
> might
> > be a serial link to a serial I/O on the RISC core.
> > Failing that it can always be memory-mapped I/O.
> That
> > will allow driver coders to get access to the
> audio
> > that is produced by the synth core, and thus do
> > further useful things with it in software, but
> these
> > are issues in which people might want to be
> involved.
> > I will probably put most of the audio modulation
> in
> > the synth core itself, thereby allowing it to be
> very
> > largely stand-alone.
> 
> I think it would be better to have a WISHBONE
> interface.
> This would ease the movement of data between your
> synthesizer
> and for example my AC97 core. We have decided a
> while back
> to adopt WISHBONE as the "standard" interconnect for
> all OC
> cores. It's not a must, but if you have to make a
> choice, than
> rather make it compatible with other OC cores. The
> RISC will
> also have a WISHBONE interface.
Yes, you are right. I realised what the WISHBONE spec
was just after I posted the message! I shall be using
that. But that is not really my major focus of concern
at the present time.

> 
> > BTW, can anyone tell me how to get the audio synth
> > core listed on the projects page?
> > 
> > Thanks
> > Miggs
> 
> Cheers !
> -- 
> rudi
> 
> 
> --
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Miggs


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