Hello,
just wanted to give my 2cents...
sure there are thousand ways to make better multipliers, moreover
current synthesis tools are pretty smart with pipelined multipliers.
One document I found very interesting is located at:
http://c3iwww.epfl.ch/teaching/webcourse/ch06/ch06.html
Anyway I reworked a little the VHDL code of Jamil, just for the fun of
it. Looks like there are some improvements in both area and speed.
Let me know what you think.
I include the .vhdl file.
Bye,
Luca.
#include <standard_disclaimer.h>
> -----Original Message-----
> From: John L. Smith [mailto:jsmith@visicom.com]
> Sent: luned́ 17 aprile 2000 19.25
> To: cores@opencores.org; Jamil Khatib
> Subject: Re: [oc] serial multiplier
>
>
> You should be able to acheive better speeds, at least with
> the Xilinx parts (what part are you targeting? 60MHz doesn't
> mean a lot without identifying device family and speed grade).
> To acheive better speed, you may have to resort to structural
> coding styles, which would vary according to the
> device family being targeted. I don't recall seeing much
> discussion of coding style in OC, and the possibility of different
> coding styles for different target devices, not to mention
> different styles for different synthesis tools..
>
> If you stay with the idea of scaling accumulation, you can halve
> the number of clock cycles by using the 'computed partial product'
> technique that Ray describes further on in the same page. This
> processes 2 bits of the multiplier at a time.
>
> To get down to one clock cycle/operand pair, it is necessary to
> 'unroll the loop', i.e., use many adders instead of a single
> accumulator,
> and pipeline everything. In the Xilinx Virtex parts, this
> pipelining is
> not very expensive, as the LUT RAM can be configured as a shift
> register to hold multiplier bits until they are required at the adder
> in which they are used. Multiplicand bits get shifted to follow
> the partial product as it accumulates through the array.
> All these techniques illustrate the common speed vs. area trade-off.
>
> Jamil Khatib wrote:
>
> > I implemented the scaling accumulator that is described in
> > http://users.ids.net/~randraka/multipli.htm
> >
> > I want to ask you how can increase its speed because teh
> best frequency
> > I reached with the best altera and Xilinx FPGAs is 60MHz for 8 bit
> > mulitplier that executes serially which meens 60MHz / 8
> throughput that
> > is too low
> >
> > Do you have any comments?
> >
> > The code is available at
> > http://www.geocities.com/SiliconValley/Pines/6639/ip/arit.html
> >
> > Thanks
> > Jamil Khatib
> >
> > __________________________________________________
> > Do You Yahoo!?
> > Talk to your friends online with Yahoo! Messenger.
> > http://im.yahoo.com
>