[oc] hello!

[=?gb2312?q?zhou=20lei?= <leizhou77@yahoo.com>]

Mr/Madam:
    I'm a student in master program in China. I major
in E.E. I'd read everything about RISC1000 & RISC2000
in your web site. I'm very interested in your idea
about RISC2000. I get several opinion. Maybe it's not
right but I hope you can give me a response.
    I think the idea of "private register of FUs" will
surely reduce the hazard in pipeline, but it will
increase the number of registers. In fact it operates
analogously to one hazard-handling method which
connects the output of ALU to other stage of the
pipeline directly to reduce the read-after-write
hazard. But the "private register of FUs" can reduce
more hazard (that is, increase more performance of
CPU) at the cost of using more register, and it dose
it with highly modularization.
    I'm sure that this idea will do, but only with
either of two precondition. First it needs an
elaborately designed instruction set & a very smart
compile software. But I think the software needs too
much AI to design. So I think more of the second
field: asynchronous CPU, like ARMulet.
    I want to do some research on RISC & pipeline CPU
recently, so I do hope you would give me a response.
After all I must thank you for your web site. It's
very valuable.
                                                 
yours lei zhou

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