Re: [oc] hello!

["Marko Mlinar" <Marko.Mlinar@campus.fri.uni-lj.si>]

> Mr/Madam:
>     I'm a student in master program in China. I major in E.E. I'd read
everything about RISC1000 & RISC2000 in your web site. I'm very interested
in your idea about RISC2000. I get several opinion. Maybe it's not right but
I hope you can give me a response.
<<<<
It's always useful to hear opinions and join forces. OC was established just
for that purpose.
>>>>

>     I think the idea of "private register of FUs" will surely reduce the
hazard in pipeline, but it will increase the number of registers. In fact it
operates analogously to one hazard-handling method which connects the output
of ALU to other stage of the pipeline directly to reduce the
read-after-write hazard. But the "private register of FUs" can reduce more
hazard (that is, increase more performance of CPU) at the cost of using more
register, and it dose it with highly modularization.
>     I'm sure that this idea will do, but only with either of two
precondition. First it needs an elaborately designed instruction set & a
very smart compile software. But I think the software needs too much AI to
design. So I think more of the second field: asynchronous CPU, like ARMulet.
>     I want to do some research on RISC & pipeline CPU recently, so I do
hope you would give me a response.

<<<<
Yes this would surely increase number of registers. But that doesn't matter
registers are very simple
components - however large register banks, with high accesibility could
bring problems.

I don't think this would be a great problem to compiler. It has to allocate
registers - if it founds out that
two registers will run on different FU and not dependent or anything, it
could just use local ones.

Local registers idea was used in or2k instead of usual register renaming,
etc to make FU smaller and
simpler.

I am looking forward to exchange some knowledge and ideas,

    Marko