[oc] Free CAD Tool

["Mark Anderson" <andersonmark@mediaone.net>]

Hey all,

    In response to the need for free CAD tools, there is one solution which
no one has mentioned (to my knowledge, I had to leave the list last week,
too many messages).

    If you don't mind doing structural design, there is a tool for FPGA's
(specifically XC4K and Virtex parts, but it's designed to be retargetable).

     It's done by BYU, and the project is called JHDL. (Just another
Hardware Description Language) It's written in Java, so it's very portable.

     The web page is http://www.jhdl.org/

     It spits out EDIF netlists which are compatible with the Xilinx
back-end tools. (Which are available free, I believe)

     The team that works on it is very active, so you can see what's
happening.

Enjoy,
  Mark