Re: [oc] some questions

["Damjan Lampret" <lampret@opencores.org>]

> ^^^
> In fact, sometimes, if your MMU goes wrong, the whole TLB may be closed.
> Then, how do you do memory access? I think we had better not let CPU
> access TLB every time the load/store insns are accessed or whenever
> insns are accessed.

If you get TLB miss then a TLB miss exception is invoked and during
exception processing there is no virtual-to-phy translation. So exception
handlers execute always with phy addresses == virtual addresses and they are
always located at some known address. Just like in PowerPC.

regards, Damjan