[oc] some questions

[jimmy87@sunplus.com.tw]

Hi ALL,
After reading stuff about OR1K from the web, www.opencores.org,
I found some questins until now.

1. no uncached region defined in OR1K? You know it's important for I/O.
2. Where are those flags?
3. no flags for privilieged-mode access? for example, kernel mode?
4. I try to use i386 gcc but segmentation fault whenever I run it.
5. It seems that or1k has only 16 GPRs(according to 4-bit reg insn encoding),
    but there are 32 GPRs in or1ksim.
6.I still don't have VHDL source codes. If it's necessary and it won't confuse
version control,
   I think I could try to convert it manually to Verilog source codes. But I
can't tell
   when I could finish it.
7. Right, what's the latency and throughput of your MUL and DIV insn? Will you
add MAC insns, for example,
    mul-and-add, mul-and-sub?
8. What's your entry replacement strategy of 64-entry unified TLBs?
9. OR1K's architecture is Harvard or VonNeumon? If Harvard, does OR1K have one
Instruction TLB, which is separated
    from 64-entry TLB?
10. Any software interrupt instructions for OS's syscalls?
11. The chip bus interface is also important for embedded usage. I still can't
see the document.
After finding more, I'll post it. Thank you!

Best regards,
Jimmy