Project: risc16f84

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Allright, here are "the goods!"


risc16f84_clk2x.v. This file contains the stripped down 16f84 microcontroller: 1 interrupt input, no watch dog timer, no port A and B, plus the Auxiliary bus (which handles much more than Ports A and B), plus it runs at 2 clock cycles per instruction.

risc16f84_small.v. This file contains the 16f84 Verilog code without EEPROM interface, with only a single interrupt input.

risc16f84_lite.v. This file contains the 16f84 Verilog code without EEPROM interface.

risc16f84.v. This file contains the full-blown 16f84 Verilog code. This file contains an example of the risc16f84_clk2x module in use. The top level module is "top.v" It uses tri-state buffers for data buses, except for the Xilinx DPRAM used to implement the 512 byte register file, which has separate data in and data out buses. There is support for hardware breakpoints, single stepping and resetting the processor through "rs232_syscon" commands given through a serial port (see opencores project at rs232_syscon).

This entire project fits into a Xilinx XC2S200 chip, taking up only about 950 slices or so, and all 14 of the DPRAM blocks (9 of the DPRAMS for a "pixel" memory for a 128 by 96 pixel display that I implemented with this project. You can remove these from the project, add new registers, create new peripherals -- whatever you like.)

NOTE: In order to get these examples to work on your own board, you will need to generate a correct BAUD clock on your board -- see the file "serial.v" for details. Also, you will need some "level translating" circuit to change the LVTTL level signals coming out of the Xilinx chip into RS232 levels for connection to your computer's serial port. Be sure to re-assign the IO constraints to match the desired pinouts on your board, and add debug outputs if you like, so that you can view what is happening on a logic analyzer... Or, you could also simulate these modules!