4. Configuration Variables

4. 1. License Server

avtLicenseServer

<string> Hostname of the machine running the license server

avtLicenseProject

<string> Project name. Used in license logging.

4. 2. Environment

avtLibraryDirs

<string> The set of library directories which are scanned for required subcircuits.

avtBlackboxFile

<string> Name of the file containing the cells to exclude of analysis.

avtCatalogueName

<string> File containing a list of subcircuits to be considered as leaf cells when flattening a design. Each line in this file refers to a single subcircuit, with the format <subcircuit> C. The default value is CATAL.

4. 3. Names

avtVddName

<string> Name of any signal or connector which is to be considered as power supply (a * in the name matches any string). Several names, separated by :, may be specified.

avtVssName

<string> Name of any signal or connector which is to be considered as ground (a * in the name matches any string). Several names, separated by :, may be specified.

avtGlobalVddName

<string> Name of an internal signal to be considered as power supply (a * in the name matches any string). Signals in different subcircuits of a hierarchical netlist with a name given here will be considered as equipotential and this name will be used in the flattened netlist. This is identical to the use of the .GLOBAL directive in a spice netlist. Several names, separated by :, may be specified.

avtGlobalVssName

<string> Name of an internal signal to be considered as ground (a * in the name matches any string). Signals in different subcircuits of a hierarchical netlist with a name given here will be considered as equipotential and this name will be used in the flattened netlist. This is identical to the use of the .GLOBAL directive in a spice netlist. Several names, separated by :, may be specified.

avtCaseSensitive

yes Upper and lower case characters are distinct
no Upper and lower case characters are seen as identical
preserve Default, upper and lower case characters are seen as identical but the original case is preserved

avtInstanceSeparator

<char> Character used to separate instance names in a hierarchical description. Default value is .

avtFlattenKeepsAllSignalNames

yes When flattening a netlist, each signal keeps all its names through the hierarchy.
no Default, only one name (the shortest) is kept per signal.

avtVectorize
Controls the internal representation of vector-signals.

yes Default, vector-signals are represented internally as vectors, as far as the vector indexation is one of [], <>, _. For example, if both foo[1], foo<1> and foo_1 appear in the source file, they will all be represented internally as foo 1
no Vector signals are represented internally as they appear in the source file.
<string> Explicits the vector-signals indexations that will be interpreted as vectors, and the represented internally as vectors. string is a comma-separated list of single or paired delimiters. For example, if string is set to "[],_", only foo[1] and foo_1 will be represented internally as foo 1.

Special attention should be paid to the Verilog case. Verilog only accepts [] as legal vector indexation. Legal verilog vectors are represented internally as vectors if avtVectorize is different to no.

Illegal Verilog vectors are supported and controlled by avtVectorize as far as they are escaped and avtStructuralVerilogVectors is set to yes. For example, \foo<1> is represented internally as a vector if avtStructuralVerilogVectors is set to yes and avtVectorize is set to <>.

4. 4. Technology

avtElpCapaLevel

Allows the user to compute differents kind of input capacitance.

0 Input capacitance is the average between up and down capacitance
1 Default, nominal up and nominal down capa are used to compute timing
2 Same behavior as if set to 1 but also minimal and maximal capacitances are computed for both transitions (6 capacitances at all).

avtTechnoModelSeparator

<char> Character that will be used as a separator between the model name and the model index. Default value is .

avtElpDriveFile

yes A ELP file specified by avtElpGenTechnoName will be printed after transistor electrical characterization.
no default

avtElpGenTechnoName

<string> Name of the generated ELP file. Default is techno.elp.

4. 5. Input Netlist and Parasitics

avtInputFilter

<string> Shell command line used to decompress an input netlist

avtOutputFilter

<string> Shell command used to compress an output file

avtFilterSuffix

<string> Suffix of the compressed files

avtDisableCompression

<string> Space separated filename list for which compression must be ignored. EXAMPLE: "*.rcx *.rep"

avtAnnotationKeepCards

transistor M character is kept before the transistor name
diode D character is kept before the diode name
resistance R character is kept before the resistance name
instance X character is kept before the instance name
capacitance C character is kept before the capacitor name
none No character is kept
all M, R, X, C, D characters are kept

avtMaxCacheFile

<int> If cache mechanisms are used, sets the maximum number of files that can be opened at the same time. Larger the value is, faster is the disk access. Default value is 128. Maximum value depend on your system (see UNIX command limit).

avtParasiticCacheSize

<int>[Kb|Mb|Gb] Size (bytes) of the memory cache for all applications dealing with parasitics. Value represents the maximum amount of information stored in memory. Increase this value to lessen disk access and speed-up application. avtParasiticCacheSize cannot be used together with compressed files.
10Mb Default
0 Disable cache and load all the parasitic information

avtFlattenForParasitic

yes Yagle flattens a hierarchical netlist in order to annotate the netlist with SPEF or DSPF parasitics. To be used together with avtCatalogueName
no default

avtVddVssThreshold

<float> Value (in volts) defining the absolute voltage value level above which a node is considered to be a power supply node. Default value is 0.5.

4. 6. SPICE Parser

avtSpiCreateTopFigure

yes Default, parser automatically creates a top-level for all elements outside of SUBCKT definition. All equipotentials are made into external connectors. The name of the top-level is the same as the filename without the extension unless a subcircuit of this name exists, in which case the name is prefixed by top_
no No top-level is created

avtSpiParseFirstLine

yes First line of all SPICE files are taken into account, unlike the behavior in standard SPICE
no First line of all SPICE files are ignored
include Default, first line of the top-level SPICE file is ignored, but the first line of included files are parsed normally

avtSpiReplaceTensionInExpressions

yes Avoids expression evaluation errors due to unhandled dynamic tensions in expression. The voltage is considered to be 0.
no Default.

avtEnableMultipleConnectorsOnNet

yes By default, there can only be one external connector per net after a netlist parse. If multiple connectors are found, they are merged into one. This can have a big drawback. Connectors required on the interface of a top level netlist can be missing. There can also be issues for ignoring instances with transparencies using hierarchical names as transparences are analysed to build nets prior to check ignored instance resistors. Setting this variable to yes allows multiple external connectors on nets so transparences are analysed during the resistor removal step without the nets being shorted already. This has an effect on ignored instances containing transparences. It affects Yagle behaviour and may make it not work in hierarchical mode.
no Default.

avtSpiMergeConnector

yes Default, connectors with the same radical, but different node indexes, will be merged (they are supposed to belong to the equipotential outside the subcircuit). The separator between the radical and the index is given by avtSpiConnectorSeparator.
no Connectors are not merged

avtSpiConnectorSeparator

<char> Character used to separate a connector radical name from its node index (ck.1, ck.2 ... for example).

avtSpiKeepNames

transistor Transistor name is kept in the database
diode Diode name is kept in the database
resistance Resistance name is kept in the database
allnodes All node names are kept for signals in the database
none No name is kept in the database
all All names are kept in the database

avtSpiKeepCards

transistor M character is kept before the transistor name
diode D character is kept before the diode name
resistance R character is kept before the resistance name
instance X character is kept before the instance name
capacitance C character is kept before the capacitor name
none No character is kept
all M, R, X, C, D characters are kept

avtSpiNameNodes

yes Default, nodes names are used rather than the node numbers
no Only node numbers are used

avtSpiNodeSeparator

<char> Character that will be used as a separator between the node name and the node number. The default value is _

avtSpiInstanceMultiNode

yes Default, allows two or more identical nodes to be declared in a subckt interface
no Only the first node declared is taken into account

avtSpiIgnoreDiode

yes Diodes are ignored by the SPICE parser.
no Diodes are characterized.

avtSpiMergeDiodes

yes Diodes are merged with neighboring transistors if the transistor is of the same type and area of the connected source or drain is 0.
no Diodes are characterized independantly.

avtSpiIgnoreVoltage

yes Voltage sources are ignored by the SPICE parser.
no Voltage sources are not ignored.

avtSpiIgnoreModel

yes Model directives are ignored by the SPICE parser.
no Model directives are not ignored.

avtSpiIgnoreCrypt

yes Encryption directives (used to indicate encrypted data) are ignored.
no The default. Encryption directives must surround encrypted test obtained by avt_EncryptSpice function.

avtSpiJFETisResistance

yes JFETs are considered to be resistances. Values are resolved by the SPICE parser.
no

avtSpiShortCircuitZeroVolts

yes Voltage sources with a value of 0 are modeled by the SPICE parser as resistances of 0 Ohms.
no

avtSpiMaxResistance

<float> If a resistance's value is greater than float (in Ohms), then the resistance is considered to be open circuit.

avtSpiMinResistance

<float> If a resistance's value is less than float (in Ohms), then the resistance is considered to be short circuit.

avtSpiMinCapa

<float> If a capacitance's value is less than float (in Ohms), then the capacitance is ignored

avtSpiOneNodeNoRc

no Removes on all nets containing only one node all parasitics information at the end of the parse.
yes

avtSpiOrderPinPower

yes Uses the name (in the same manner as avtSpiDspfBuildPower) of the instance nodes to ensure a correct order for power supply connectors.
no

avtSpiFlags
This configuration is used to control the behavior of the spice parser/driver. The values (flags) are added separated with commas.

DriveInstanceParameters Enables the drive of the instances with all their parameters
IgnoreGlobalParameters Works with DriveInstanceParameters and removes all the global parameters from the instance parameters to drive. Useful when the netlist has been flattened and the parameters inherited by the leaf instances.
KeepBBOXContent Will keep the content of the figures set as blackboxes whereas by default only the interfaces are kept.
TransfertTopLevelVcards Will transfert voltage sources connected to instances, who are defined out of a subckt in the spice file, in their corresponding circuit subckt so the Vcards can be taken into account when working on one of this instance circuit. This option is enabled by default. It can be unset by adding '!' in front of the option: '!TransfertTopLevelVcards'.
ExplicitInstanceNames If enabled then instance names specified in the netlist are prefixed by the subckt name in order to create the internally used name.

avtSpiTolerance

This variable tunes the tolerance of the SPICE parser regarding unrecognized syntaxes for R (resistances) and C (capacitances) devices.

low Parser exits when encountering unknown syntax
medium Parser continues and tries to keep only the nominal value of the device, issuing a warning message
high Same as in the medium configuration, but no warning message is issued

avtSpiHandleGlobalNodes

yes Default, global nodes defined in spice netlist without resistances will be considered equipotential.
no

4. 7. SPICE Driver

avtSpiVector

_ Default, vectors are of the shape foo_1 in output spice files
[] Vectors are of the shape foo[1] in output spice files
() Vectors are of the shape foo(1) in output spice files
<> Vectors are of the shape foo<1> in output spice files

avtSpiDriveDefaultUnits

<string> Its behavior is to indicate the parameter units to be used when instantiating a transistor. For instance, avtSpiDriveDefaultUnits = W:1e-6;L:1 will set the spice driver to drive parameter W value in micron and parameter L in meter.

avtSpiUseUnits

yes Allows the use of units in driven spice files. This is the default.
no

avtSpiDriveParasitics

yes A SPEF file will be generated while parsing a SPICE file. The loaded file will be stripped of all resistors and capacitors. The SPEF file can be used as a parasitic cache file.
no

avtSpiDriveTrsInstanceParams

no Specifics instances parameters for the models of transistors will not be driven.
yes

avtSpiDriveCapaMini

<float> When driving a Spice netlist, doesn't drive capacitances below float (in Pico-farads). Default is 10-6 pF.

avtSpiDriveResiMini

<float> When driving a Spice netlist, fix minimum value for resistances to float (in Ohms). Default is 10e-3 Ohms.

avtSpiRCMemoryLimit

<int> Amount of memory in MB allowed to creating a .SPEF file from a spice file. This option influences avtSpiDriveParasitics speed. The default value is 100.

avtSpiFlags
This configuration is used to control the behavior of the spice parser/driver. The values (flags) are added separated with commas.

DriveInstanceParameters Enables the drive of the instances with all their parameters
IgnoreGlobalParameters Works with DriveInstanceParameters and removes all the global parameters from the instance parameters to drive. Useful when the netlist has been flattened and the parameters inherited by the leaf instances.
KeepBBOXContent Will keep the content of the figures set as blackboxes whereas by default only the interfaces are kept.
TransfertTopLevelVcards Will transfert voltage sources connected to instances, who are defined out of a subckt in the spice file, in their corresponding circuit subckt so the Vcards can be taken into account when working on one of this instance circuit. This option is enabled by default. It can be unset by adding '!' in front of the option: '!TransfertTopLevelVcards'.

4. 8. VHDL Parser/Driver

avtVhdlMaxError

<int> Maximum number of errors before the VHDL structural parser abandons.

avtStructuralVhdlConfigure

yes VHDL structural driver generates the appropriate configuration statement to allow simulation.
no Default

avtStructuralVhdlSuffix

<string> Suffix of VHDL structural (netlist) file. The default is vhd

avtBehavioralVhdlSuffix

<string> Suffix of VHDL behavioral file. The default is vhd

4. 9. VERILOG Parser/Driver

avtVerilogKeepNames

yes When generating Verilog output, any internal names which are not legal verilog names are preceded by a double backslash.
no Default. Illegal names are modified to create a legal name.

avtStructuralVerilogVectors
Affects the parsing of illegal Verilog vector-signals in a netlist, i.e. vector-signals that are not indexed using the [] characters. Illegal Verilog vector-signals are supported as long as they are preceded by \, otherwise the Verilog parser issues a syntax error. Legal Verilog vector-signals are controlled by avtVectorize.

yes Force illegal Verilog vector-signals to be represented as vectors in the internal database, with regard to the value of avtVectorize. For example, \foo<1> is represented internally as foo 1 if avtVectorize is set to <1>
no Default, illegal Verilog vector-signals are represented in the internal database as they appear in the file. For exemple, \foo<1> is represented internally as foo<1>

avtStructuralVerilogSuffix

<string> Suffix of Verilog structural (netlist) file. The default is v

avtBehavioralVerilogSuffix

<string> Suffix of Verilog behavioral file. The default is v

avtVerilogMaxError

<int> Maximum number of errors before the Verilog parser abandons.

4. 10. DSPF/SPEF Parser

avtAnnotationPreserveExistingParasitics

yes Existing parasitics on nets annotated in a DSPF/SPEF file won't be overridden by the parasitics in the DSPF/SPEF file. The DSPF/SPEF information will rather be added to the existing ones.
no Default

avtAnnotationDeviceConnectorSetting

<string> Overrides the internal tool known device connector names used in DSPF/SPEF annotation. The string must contain 10 items in the following order: transistor source name, transistor gate name, transistor drain name, transistor bulk name, resistor positive connector, resistor negative connector, capacitor positive connector, capacitor negative connector, diode positive connector, diode negative connector. By default, the tool knows of "s g d b 1 2 1 2 1 2" and "s g d b pos neg 1 2 1 2".

Example:

avt_config avtAnnotationDeviceConnectorSetting "src gate drn blk 1 2 1 2 1 2"

avtSpiDspfBuildPower

yes Only used for DSPF annotation. When creating a figure from DSPF information, use the avtGlobalVddName, avtGlobalVssName, avtVddName and avtVssName to detect power connections on the instance, so they are created on the boundary of it instead of being merged with all unknown connectors.
no

avtSpiDspfLinkExternal

yes Only used for DSPF annotation. When an external connector is not connected to anything, and if there is an internal signal with the same name, then the connector is assumed to be on this signal.
no

avtSpiPinDspfOrder

yes Only used for DSPF annotation. Order of connector of an instance is the one described in the DSPF instead of the one described for the instance interface.
no

4. 11. General Configuration

yagHierarchicalMode

yes Activates the hierarchical disassembly mode.
no Default

yagWriteStatistics

yes Statistics of detected power supplies and particular transistor configurations are saved in a file with the suffix .stat.
no Default

yagMutexHelp

yes An algorithm which attempts to guess any misssing MUTEX constraints is activated. Groups of signals which could have constraints are reported in a file of suffix .mutex.
no Default

yagSearchLoops

yes An algorithm to detect combinatorial loops of more than two gates is activated. Any loops detected are reported in a file of suffix .loop.
no Default

yagDebugCone

<string> If set to the name of a cone, then additional debug information for that cone is displayed.

yagNotStrict

yes Certain aspects of the net-list coherency are not verified, such as un-driven transistor gates.
no Default

yagElpCorrection

yes Updates the capacitances to take into account technology dependant factors, such as diffusion capacitance, gate capacitance and shrink.
no Default

yagSuppressBlackboxes

yes Reads a hierarchical net-list in which some of the instances are considered to be black boxes (i.e. their internal structure is unavailable). The list of these instances is given by the user in a file whose name is given by avtBlackBoxFile. Yagle creates a new intermediate netlist containing only the non-black box instances, and modifies the original net-list to instantiate this new figure and the black box instances. The modified original netlist is saved to disk, and the functional abstraction is performed on the intermediate figure.
no Default

yagIgnoreBlackboxes

yes Reads a hierarchical netlist in which some of the instances are considered to be black boxes. The name of these instances is given in a file whose name is given by avtBlackBoxFile. The hierarchical netlist is then flattened to the transistor level apart from the black box instances to generate a hybrid transistor and instance netlist. The functional abstraction is performed on this hybrid netlist.
no Default

yagRemoveInterconnects

yes Deletes parasitic information before performing desassembly and functional abstraction.
no Default

yagSilentMode

yes Yagle does not write anything to the standard output.
no Default

4. 12. Disassembly

4. 12. 1. Functional Analysis

yagAnalysisDepth

<int> Allows the user to set the depth for the functional analysis. This is the number of gates that will be taken into account for the functional analysis, so that Yagle can detect re-convergence in the circuit. Default is 7.
0 Functional analysis process is disabled

yagHzAnalysis

yes Allows functional analysis through high impedance nodes.

yagMaxBranchLinks

<int> Maximum number of links in a cone branch.

yagRelaxationMaxBranchLinks

<int> Used to limit the maximum number of links for the difficult gates for which functional dependencies could not be resolved.

yagBddCeiling

<int> Limits the maximum number of BDD nodes which are allowed to be created for the resolution of any Boolean expression. If this limit is exceeded the operation is abandoned. Default is 10 000.

yagElectricalThreshold

<float> Used in electrical resolution of conflicts to determine the zones corresponding to the high, low and conflictual states. Default is 4, implying that the high and low states are represented by zones 1/4 of the zone Vss-Vdd.

yagUseStmSolver

yes Precise current calculations using technology files are used in electrical conflict resolution.
no Default, basic transistor dimensions are used in electrical conflict resolution.

yagRelaxationAnalysis
During the gate construction phase, Yagle attempts to resolve all functional dependencies before building a particular gate. However, in particular cases of looped dependencies, this may not be possible for all gates.

yes Functional dependencies are ignored to resolve these gates.
no Default, Yagle tries to use as much information as possible.

yagDetectGlitchers

yes A branch containing two transistor with mutually exclusive gate drivers and which cannot be part of another gate are assumed to exist dynamically. They are therefore not removed by the functional analysis. This is the default.
no

yagKeepRedundantBranches
For any CMOS dual cones extracted, if supplementary branches are added at a later stage of the disassembly and the gate remains non-conflictual, then these branches are considered to be functionally redundant.

yes The branches are kept.
no Default, the branches are removed.

yagPullupRatio

<float> Used in the detection of pull-up or pull-down resistance transistors. Default is 10, implying that a transistor is a pull-up if an estimation of its resistance is greater than 10 times the resistance of the most resistive current path to ground. Similarly for pull-pown resistances.

4. 12. 2. Transistor Orientation

yagSimpleOrientation

yes Activates a simple transistor orientation heuristic. Can sometimes accelerate the disassembly, however, it is more robust to rely exclusively upon the functional analysis.
no Default.

yagUseNameOrientation

yes Exploits the _s naming convention for transistor orientation.
no Default.

yagBlockBidirectional

yes Bidirectional transistors are not allowed.
no Default.

yagCapacitanceCones

yes Default. Build cones on nodes with only capacitances. Necessary to calculate the out of path capacitance.
no Disables construction of cones on only capacitance nodes.

yagTestTransistorDiodes

yes Default. Any transistor with the gate shorted to a source or a drain is considered as a diode.
no Disables diode detection.

yagMutexHelp

yes A file with extension '.mutex' is generated containing help for MUTEX settings on external pins or memory nodes necessary to correctly orient the transistors.
no Default.

4. 12. 3. Latch Recognition

yagSimpleLatchDetection
A simple structure based recognition algorithm which handles the various cases of double inverter loops. This approach is not usually required and is not guaranteed to be formally correct but can sometimes help in cases where the automatic approach is too CPU intensive. The following values can be given for this variable:

memsym Double inverter loops are also analyzed to see if they correspond to a simple symmetric bitcell. In this case the the command of the bitcell is the input of the pass transister or transfer gate connected directly to the loop.
levelhold Double inverter loops are considered to be level-hold or buskeeper structures (i.e. not latches).
strictlevelhold Double inverter loops are considered to be level-hold or buskeeper structures (i.e. not latches), but only if only one side of the inverter loop is connected.
latch Double invertor loops are treated as latches without any anlysis, unless a level-hold or memsym option is also activated and these forms match. Commands are guessed without analysis. This option helps if double inverter loops are used to latch the output of complex multiplexors.

The above options can be concatenated by separating the individual options with a '+' character. However the combinations "levelhold+strictlevelhold" and "levelhold+latch" make no sense. The search options are applied in the order specified above. By default all the options are disabled.
yagAutomaticLatchDetection

yes Advanced latch detection algorithm based on Boolean loop analysis is activated. Default.
no Advanced latch detection is disabled.

yagSetResetDetection

yes Only works with yagAutomaticLatchDetection set to yes. Asynchronous latch commands are marked asynchronous instead of being marked commands. False timing arcs (corresponding to the conditioning of data by an asyn or the conditioning of an async by a clock) are disabled.
remove Does the same as the yes mode. In addition marks as non-functional any branches corresponding to an asynchronous write.
no Default.

yagAutomaticRSDetection

mark Default. Only works with yagAutomaticLatchDetection set to yes. Supplementary RS bistable detection algorithm is applied to automatically detected latches. Only NAND/NOR types are accepted. Any detected RS bistable loops will be marked and reported but not treated as latches.
no Automatic RS detection is disabled. Recognition depends upon yagAutomaticLatchDetection
mark+latch One of the gates of the loop is considered a latch. The latch is the gate with the largest number of outputs.
mark+legal The algorithm assumes that an RS structure always remains in its legal states. Timing arcs are suppressed accordingly. For NOR-based RS, the following timing arcs are suppressed: S(f) to QB(r), R(f) to Q(r), QB(r) to Q(f) and Q(r) to QB(f). For NAND-based RS, the following timing arcs are suppressed: S(r) to QB(f), R(r) to Q(f), QB(f) to Q(r) and Q(f) to QB(r).
mark+illegal The algorithm assumes that an RS structure may enter an illegal state. Less timing arcs are suppressed than when the tool assumes that an RS structure always remains in its legal states. For NOR-based RS, the following timing arcs are suppressed: Q(r) to QB(f) and QB(r) to Q(f). For NAND-based RS, the following timing arcs are suppressed: Q(f) to QB(r) and QB(f) to Q(r).

yagAutomaticMemsymDetection

yes Only works with yagAutomaticLatchDetection set to yes. Supplementary symmetric memory detection algorithm is applied to automatically detected latches. Symmetric memories are memorizing elements such as bitcells for which data is written in both or either side of the memorizing loop. Both sides of the loop are marked as latches is order to verify all cases.
no Default.

yagDetectDynamicLatch

yes Internal tri-state nodes are considered to be dynamic latches for functional modeling and timing analysis purposes. A special algorithm, similar to that used in the automatic latch detection, is used to identify the latch commands and generate an accurate latch model.
no Default.

yagDetectPrecharge

yes An algorithm designed to detect automatically most kinds of precharge nodes is activated. The algorithm is particularly designed for domino precharge style designs.
no Default.

yagBleederStrictness

A level between 0 and 2 defining the strictness of the bleeder detection algorithm. The value determines the kind of gate which can be tolerated in the bleeder loop.

0 any CMOS gate is acceptable
1 default, any CMOS dual gate is acceptable
2 it must be an inverter

yagStandardLatchDetection
Deprecated. This structure based latch recognition technique is activated by default as a catch-all. It will probably be removed in a future version.

yes Default, standard latch detection algorithm is activated.
no Standard latch detection algorithm is disabled.

yagLatchesRequireClocks

yes Any latch which does not have a command which is at the end of a path from a specified clock is not considered to be a latch. If this option is used, then extreme care should be taken to specify the clocks to avoid problems in any subsequent analysis.
no Default.

yagDetectClockGating

yes If clocks are configured before the disassembly phase then reconvergence between clock and data will be detected, appropriate timing check and data filtering directives are automatically generated.
check Same as above except only the timing checks are added.
filter Same as above except only the data filtering directives are added.
no Default.

yagDetectDelayedRS

yes Detect special type of NAND/NOR bistable loop structure containing additional inverters to add delay in the loop. Results in the same handling as the legal setting for RS detection. This type of structure is commonly used to generate non-overlapping clocks.
no Default.

4. 12. 4. Pattern Matching

yagUseGenius

yes Extends the simple pattern recognition of FCL to allow the recognition of hierarchically defined structures of generic size.
no Default

yagUseOnlyGenius

yes Same as yagUseGenius but Yagle stops the execution after the hierarchical pattern recognition phase.
no Default

4. 12. 5. Behavioral Model Generation

yagTasTiming

max delay information is calculated for annotation of the data flow description using timing characterization with worst case timings
med delay information is calculated for annotation of the data flow description using timing characterization with average timings
min delay information is calculated for annotation of the data flow description using timing characterization with best case timings

yagSplitTimingRatio

<float> Used if a timed behavioral model is generated. Models for some auxiliary signals will be enhanced to differentiate up and down transitions. This operation is performed if one of the transitions has a delay greater than float times the other. If the value is less than 1 then this operation is never performed. Note that this option should not be used if a Verilog behavioral model is to be generated sice verilog timings always contain this differentiation. The default value is 0.

yagSensitiveTimingRatio

<float> Used if a timed behavioral model is generated. Models for some auxiliary signals will be enhanced to differentiate the timing according to the input which actually changes. float corresponds to the minimum ratio between the greatest and the least timing value above which the operation is performed. If the value is less than 1 then this operation is never performed. The default value is 0.

yagMaxSplitCmdTiming

<int> Used if a timed behavioral model is generated. Models for some busses or register signals will be enhanced to differentiate the timing according to each input combination which can change the value. int corresponds to maximum number of combinations under which the differentiation is applied. The default value is 0 (disabled).

yagSensitiveTimingDriverLimit

<float> Used to set an upper limit to the number of expression inputs for which yagSensitiveTimingRatio has an effect. If expression depends on mare variables than this limit the sensitive timing expression is not generated. Used to avoid unwieldy models for complex multiplexor structures.

yagOneSupply

yes Only one power supply and ground connector is defined in the interface of the behavioral description.
no Default

yagNoSupply

yes Disables dumping of power supplies declaration into generated behavior.
no Default

yagReorderInterfaceVectors

yes All bussed connectors on the interface of the design being modelled are re-ordered such that they are defined as vectors with most significant bit first.
no Default. Interface connectors are left in the order of the original design.

yagBleederIsPrecharge

yes Bleeders are modeled as nodes which maintain their value.
no Default

yagTristateIsMemory

yes Internal high impedance nodes are modeled as nodes which maintain their value.
no Default

yagAssumeExpressionPrecedence

yes Signals with multiple drivers are modeled using a single cascaded IF statement, hence a precedence is assumed.
no Default

yagSimplifyExpressions

yes Boolean expression simplification is performed on the final model.
no Default

yagSimplifyProcesses

yes Simplifies the expressions of the behavioral data flow processes.
no Default

yagMinimizeInvertors

yes Chains of invertors are reduced in the final model.
no Default

yagCompactBehavior

yes A compaction algorithm is applied on the generated model capable of generating vectorized and looped assignations in order to reduce the size of the code.
no Default

yagBusAnalysis

yes Uses a functional analysis algorithm to distinguish individual drivers of bussed signals.
no Default

yagDriveConflictCondition

yes Latches and bussed signals for which a conflict condition is detected after all analysis are modeled with this conflict condition.
no Default. The conflictual condition is ignored.

yagDriveAliases

yes Drives a file with the extension .aliases with information on the circuit hierarchy. This file is used when using the tool avt_vcd2hvcd.tcl that rebuild a hierarchical .vcd from from a flat .vcd file.
no Default. No file generated.

4. 12. 6. Cone Output Files

avtVerboseConeFile

yes Generating a .cnv cone file result in a more readable version but which is not suited for GUI vizualisation.
no Default.

avtNormalConeFile

yes A normal .cns cone file is produced.
no Default.

avtFullConeFile

yes .cnv or .cns cone files are generated with parasitic information.
no Default.

yagGenSignature

yes Signatures are generated for each cone which are used to associate icons with the cones.
no Default.

4. 13. Output Configuration

yagOutputName

<string> Name given to the generated behavioral data flow description
no Default

yagGeniusTopName

<string> Name given to the root structural figure of a hierarchical netlist generated as a result of GNS

yagGenerateBehavior

yes Default, generates the behavioral data flow description.

yagGenerateConeFile

yes A .cns file is generated, giving details of the disassembled gates
no Default

yagGenerateConeNetList

yes Generates a structural description of the disassembled gates together with a behavioral model for each distinct gate type
no Default

yagHierarchyGroupTransistors

yes In hierarchical abstraction mode, any transistors left in an otherwise fully modeled design hierarchy, are grouped together and abstracted as if they were in their own subckt.
no Default. Any transistors left over will be driven as such (in verilog) or ignored (in vhdl).

avtOutputBehaviorFormat

vhd Output behavior format is VHDL
vlg Output behavior format is Verilog

avtOutputBehaviorVectorDirection

TO Vector signals generated by BEG functions will be expressed from the lower bound to the higher bound
DOWNTO Default, vector signals generated by BEG functions will be expressed from the higher bound to the lower bound

4. 14. Pattern Matching

fclLibraryName

<string> Name of the file containing the list of cells in the user-defined cell library used. The default is LIBRARY.

fclLibraryDir

<string> Access path to the directory containing the user-defined cell library used. Default is a directory /cells in avtWorkDir.

fclGenericNMOS

<string> A colon separated list of transistor model names which the FCL pattern-matching engine considers will match to any N-type transistor. If a pattern netlist contains non-generic N-channel transistors then these transistors will only match to transistors with an identical model. Default is tn:TN.

fclGenericPMOS

<string> A colon separated list of transistor model names which the FCL pattern-matching engine considers will match to any PMOS transistor. If a pattern netlist contains non-generic P-channel transistors then these transistors will only match to transistors with an identical model. Default is tp:TP.

fclWriteReport

yes A correspondence file is created if the -fcl option is used. This file details all the recognized instances.
no Default

fclAllowSharing

yes Matched cells are allowed to share transistors.
no Default

fclCutMatchedTransistors

yes Matched transistors are eliminated from the transistor netlist. Results in a strict partitioning of the cones and the matched cells.
no Default

fclMatchSizeTolerance

<int> Percentage tolerance for matching transistor sizes.

fclTraceLevel

<int> Number greater than 0. Trace information is displayed during the pattern-matching phase.

fclDebugMode

<int> Number greater than 0. Additional debugging information is displayed during the pattern-matching phase.

4. 15. Hierarchical Pattern Matching

gnsLibraryName

<string> Name of the file (recognition library) containing the list of cells to recognize. Default is LIBRARY.

gnsLibraryDir

<string> Access path to the directory containing the recognition library. Default is directory cells/ in avtWorkDir.

gnsKeepAllCells

yes All matched structures are extracted from the netlist.
no Default

gnsTemplateDir

<string> Directory where to find the GNS templates. Default is $AVT_TOOLS_DIR/gns_templates.

gnsTraceLevel

<int> From 0 to 6. Indicates the level of trace displayed during the recognition phase. Default is 0.

gnsTraceFile

<string> Name of the output trace file. Default is stdout.

gnsTraceModel

<string> When tracing the recognition, indicates the name of the recognized model to trace. If not specified, traces all models.

gnsFlags
This configuration controls the behavior of GNS. The values (flags) are added separated with commas. Available flags are:

EnableCore Enable the generation of a core file for a crash in a user compiled API.
NoGns Disables the generation of the .gns file
VerboseGns Produces a more readable .gns file.
NoOrdering Disables the top-level instance connectors reordering. Should not be set if using the BEG functions.

4. 16. API Specific

apiFlags
Controls the behavior of the GNS API. The values (flags) are added separated with commas. Available flags are:

ttvUseInstanceMode Sets the TTV functions to generate/use one timing view per instance of the same matched subcircuit.
ttvDriveDTX Enables the drive of the .dtx and .stm files for timing views created with the TTV functions

apiDriveCorrespondenceTable

yes Correspondence table between behavioral names and electrical names has to be driven (.cor file)
no Default

apiUseCorrespondenceTable

yes Use the signal correspondance to revert the driven signals to their corresponding name in the original netlist. It removes the artificially created GNS hierarchical names.
no Default

apiDriveAllBehavior

yes All the generated behaviors will be driven.
onlymodel Only the first instance of each model will be driven
no Default

4. 17. GUI

xyagIconLibrary

<string> Full path of a specific .slib icon library

xyagMakeCells

yes Complex gates are represented using a single icon
no Default