2. Output Files

2. 1. DTX - The Detailed Perfmodule Format

2. 1. 1. Description

The DTX format is used to report gate or interconnection delay details. The file has the extension .dtx. This format is also known as the 'detailed perfmodule'. This is a highly compact text format suitable for flat and hierarchical analysis. The content is best visualized with a Tcl interface, or with the XTAS GUI.

2. 1. 2. Units

Unless otherwise stated, all capacitances are given in Femto-farads, all times are given in picoseconds, and all resistances are given in ohms.

2. 1. 3. Comments

Any line starting with the '#' character is considered to be a comment.

2. 1. 4. Articles

The 'detailed perfmodule' contains several articles and is terminated by the 'G' article.

Information Header

General information is given in a single 'H' article at the beginning of the file :

H <tool> <vers> <name> <techno> <techno_vers> <inslope> <outcapa> <hierarchy_level> (<day> <month> <year> <hour> <minute> <second>);

Instances

Instances in a hierarchical figure are given in 'X' articles :

X <figure_name> <instance_name>;

External Connectors

External connectors are given in 'C' articles :

C <type> <index> <name> <netname> <capa>;

The 'type' defines the connector direction and whether it is the command of a register or a precharge. It can be one of :

I for an input connector
O for an output connector
B for a bidirectional connector
T for a transceiver connector
Z for a high-impedance connector
X for an unconnected connector
IQ input connector used as command for register or precharge
BQ output connector reused as input to command register or precharge

The electrical parameter given for each connector is :

capa capacitance attached to connector

Internal Connectors

Internal connectors are given in 'N' articles :

N <type> <index> <name> <netname> <capa>;

The 'type' defines whether it is the command of a register or a precharge. It can be one of :

I not used as command for register or precharge
Q used as command for register or precharge

The electrical parameter is the same as those for external connectors.

Register or Precharge Commands

Commands of registers and precharges are given in 'Q' articles :

Q <type> <index> <name> <netname> <capa> (<cmd1> <cmd2> ... );

The 'type' can be one of the following :

C for an external connector command (also an external connector)
N for an internal connector command (also an internal connector)
E for an external command (extremity of an external path)
I for an internal command (not the extremity of an external path)

The list of command names in brackets is the list of commands lower down in the hierarchy which are internal or external commands and which have been replaced by this command at the current hierarchical level. Thus the command attribute of an arc can be defined at each level in the hierarchy.

Registers

Registers are given in 'L' articles :

L <type> <index> <name> <netname> <capa>;

The 'type'is XY where x can be L, F, R or S and Y can be C, N, E, I :

L stand for latch
F stand for flip-flop
R stand for nand set reset latch
S stand for nor set reset latch
C an external connector register (also an external connector)
N an internal connector register (also an internal connector)
E an external register (extremity of an external path)
I an internal register (not the extremity of an external path)

The list in brackets is the list of command events which allow the opening of a level-triggered register or the writing into an edge-triggered register. The 'index' represents the index of the command signal. The type can be one of :

U for a rising-edge event
D for a falling-edge event
Y for 0 to HZ event
Z for 1 to HZ event

Precharged Signals

Precharged signals are given in 'R' articles :

R <type> <index> <name> <netname> <capa>;

The 'type' can be one of :

C for an external connector precharge (also an external connector)
N for an internal connector precharge (also an internal connector)
E for an external precharge
I for an internal precharge

Break

Breaks are given in B articles:

B <type> <index> <name> <netname> <capa>;

The 'type' can be one of:

C for an external connector precharge (also an external connector)
N for an internal connector precharge (also an internal connector)
E for an external precharge
I for an internal precharge

Factorization Points

Factorization points are given in 'I' articles :

I <type> <index> <name> <netname> <capa>;

The 'type' can be one of :

E for an external factorization signal
I for an internal factorization signal

Other Signals

Any other signals are given in 'S' articles :

S <type> <index> <name> <netname> <capa>;

The 'type' can be one of :

E for an external signal
I for an internal signal

Elementary Delays

Delays represented by one of three 'delay_type' articles. These are :

F for an elementary delay which is only part of paths internal to the figure.
E for an elementary delay which is part of at least one path external to the figure.
D for an elementary delay which has a connector as an extremity.

The general syntax of these articles is :

<delay_type> <starttype> <start> <endtype> <end> (
(<cmd> <cmdtype> (<trs> <type> <delay> <slope> <model(s)>))
( . . (. . . . .))
);

where the parameters represent :

starttype type of the signal at the start of the path (C, N, Q, L, R, I, S).
start index of the start signal.
endtype type of the signal at the end of the path (C, N, Q, L, R, I, S).
end index of the end signal.
cmd index of command if end is register or precharge
cmdtype type of event which activates command (U or D).
trs transition type from event1 to event2, where an event can be one of the following: U for 0-to-1 event, D for a 1-to-0 event, Z for a 0-to-HZ event, Y for a 1-to-HZ event.
type delay type (SMAX, SMIN, HMAX, HMIN, AMAX, AMIN, IMAX, IMIN, MAX or MIN). With SMAX and SMIN for set-up, HMAX and HMIN for hold, AMAX and AMIN for Access and MAX and MIN for delay, IMAX and IMIN for interconnect delay
delay propagation delay.
slope slope at end.
model(s) one delay model (and one slope model).

2. 2. STM - The Models Format

2. 2. 1. Description

The STM format is used by the timing analyzer HITAS to report delay and slope models. The file has the extension .stm.

2. 2. 2. Articles

The STM file contains a header and a list of models. These models are delay and slope models. Models refer to timing arcs and timing paths.

lookup table model:

model (
   name (modelname)
   vth (value) #measure threshold
   vdd (value) #power supply
   vt (value)  #vt transistor
   vf (value)  #final voltage
   spline (                             # 2D table
      input_slope_axis (value value value)
      load_axis (value value value)
      data (                      #        load
         (value value value)      #      --------->
         (value value value)      # slope|
         (value value value)      #      |
      )                           #      V
   )
)

"SCM" model:

model (
   name (modelname)
   vth (value) #measure threshold
   vdd (value) #power supply
   vt (value)  #vt transistor
   vf (value)  #final voltage
   scm_dual (
      dual (
         (<list_of_parameter_names>)
         (<list_of_parameter_values>)
      )
   )
   noise_scr(val) #noise parameter
)

pconf0, pconf1: conflict capacitance parameters
capai: intrinsic capacitance
irap: currant ratio
vddin: input voltage
vt: vt transistor
threshold: measure threshold
imax: max currant
an, bn: specifical parameters
vddmax: power supply
rsat: saturation resistance
rlin: linear resistance
drc: intrinsic RC delay

scm_good model example:

scm_good (
   link_out (
      (ci cf k3 k4 k5)
      (val val val val val)
   )
   link_dual (
      (ci cf acti bcti)
      (val val val val)
   )
   dual (
      (<list_of_parameter_names>)
      (<list_of_parameter_values>)
   )
)

scm_false model example:

scm_false (
   link_out (
      (ci cf k3 k4 k5)
      (val val val val val)
   )
   false (
      (pconf0 pconf1 rtot kf vddmax)
      (val val val val val)
   )
)

scm_path model example:

scm_path (
   link_out (
      (ci cf k3 k4 k5)
      (val val val val val)
   )
   path (
      (pconf0 vddmax)
      (val val)
   )
)

2. 2. 3. Units

Unless otherwise stated, all capacitances are given in Femto-farads and all times are given in picoseconds.

2. 3. STO - STA Output Format

The .sto file is an ASCII text file made up of six distinct sections. This file is generated by HITAS and is intended mainly for debugging purposes, since for most purposes, the setup and hold slacks given in the timing report are sufficient. The six sections are:

Apart from the general header, some of the sections may be omitted if they are of no relevance.

2. 3. 1. Input Connector Switching Windows

This section gives the switching windows at the input connectors.

The syntax is as follows:

input connectors stability
begin
  <input1> [from <phase>]:
    unstable <value>;
    stable   <value>;
        |    |
        |    |
  <inputn> [from <phase>]:
    unstable <value>;
    stable   <value>;
end;

2. 3. 2. Memory Signals Switching Windows

This section specifies the switching windows at all memory signals.

The syntax is as follows:

memory nodes stability
begin
  <node1> [from <phase>]:
    unstable <value>;
    stable   <value>;
        |    |
        |    |
  <noden> [from <phase>]:
    unstable <value>;
    stable   <value>;
end;

This section gives the switching windows calculated for all memory signals.

2. 3. 3. Internal Signals Switching Windows

This section specifies the switching windows at all internal signals, except memory signals.

The syntax is as follows:

internal nodes stability
begin
  <node1> [from <phase>]:
    unstable <value>;
    stable   <value>;
        |    |
        |    |
  <noden> [from <phase>]:
    unstable <value>;
    stable   <value>;
end;

This section gives the switching windows calculated for all signals, except memory signals. If the analysis is performed on the timing path graph (the default), the section is empty. If the analysis is performed on the timing arcs graph, then the set includes all signals.

2. 3. 4. Output Connector Switching Windows

This section specifies the switching windows at the output connectors.

The syntax is as follows:

output connectors stability
begin
  <output1> [from <phase>]:
    unstable <value>;
    stable   <value>;
        |    |
        |    |
  <outputn> [from <phase>]:
    unstable <value>;
    stable   <value>;
end;

This section gives the switching windows calculated for outputs. This is the data which is compared with the output connector constraints specified in the '.inf' file or in the Tcl script, to calculate the setup and hold slacks. Every output connector is specified explicitly.

Note that, unlike the output specifications, it is the phase of origin which is given. The destination phase obviously cannot be deduced.

2. 4. STR - STA Report Format

For most users, this is the most important file generated by HITAS. It has the suffix .str and a base name identical to that of the original subcircuit. It lists the setup and hold slacks calculated for all reference points. This includes:

All memory and conditioned commands are specified with the details of propagated clock, since this is the reference for the setup and hold calculations.

A negative value for a setup or hold slack indicates a violation. In the event of a violation on a particular signal, all data sources resulting in a violation are listed for that signal, together with their individual setup and hold slacks.

2. 5. CTK - Crosstalk Report Information

The .ctk file is an ASCII text file made up of three distinct sections. This file contains the following information:

2. 5. 1. Delay Changes due to Crosstalk

This section reports all delay and slopes which have changed due to crosstalk. Thresholds for slope and delay changes can be set to avoid excessive reporting information. These thresholds are set using the ctkDeltaDelayMin and ctkDeltaSlopeMin configuration variables.

The syntax of this section is as follows:

BeginDelay
  UP|DW <start> UP|DW <end>
     delay|slope min|max <nominal> -> <aggressed>
         |      |
         |      |
     delay|slope min|max <nominal> -> <aggressed>
   |
   |
  UP|DW <start> UP|DW <end>
     delay|slope min|max <nominal> -> <aggressed>
         |      |
         |      |
     delay|slope min|max <nominal> -> <aggressed>
EndDelay

Fields <start> and <end> represent timing signal names. If the timing signal name is different from the net name, then the net name is given in brackets. Fields <nominal> and <aggressed> represent delay values in picoseconds without and with crosstalk respectively.

2. 5. 2. Detailed Aggression Report

This section gives detailed aggressor information for nets whose total coupling capacitance exceeds a certain threshold. The coupling capacitance due to each aggressor is given, as well as information as to whether the aggressor can modify minimum or maximum delays. Only nets for which the relative coupling capacitance is greater than the ctkrcapamin configuration variable are reported.

The syntax of this section is as follows:

BeginCrosstalk
  Node: DW|UP <signal> 
    Ground capacitance: <value>
    Aggressor:
      [*] <signal> [B] [W] [R] [F] cc=<value>
             |         |
             |         |
      [*] <signal> [B] [W] [R] [F] cc=<value>
                                     ---------
                                     <total> (<relative>)
  |
  |
  Node: DW|UP <signal> 
    Ground capacitance: <value>
    Aggressor:
      [*] <signal> [B] [W] [R] [F] cc=<value>
             |         |
             |         |
      [*] <signal> [B] [W] [R] [F] cc=<value>
                                     ---------
                                     <total> (<relative>)
   EndCrosstalk

If a star (*) is present before an aggressor name, it mean that there is no corresponding timing signal. As no switching information is provided for this aggressor, the crosstalk engine assumes that this aggressor is always an active aggressor.

If the character 'B' or 'W' or both are present on a line, this means that the aggressor can modify minimum propagation delays (B = Best Case) or maximum propagation delays (W = Worst Case). If the character 'R' or 'F' or both are present on a line, this means that the aggressor has made a contribution to calculate the real rise (R) peak noise voltage value or the real fall (F) peak noise voltage value. These characters can appear in lower case ('b','w','r','f') when crosstalk mutex are used. This means the influence of the net is ignored because of the crosstalk mutex. The total value of the coupling capacitance and it relative contribution to the total net capacitance is also given.

2. 5. 3. Peak Noise Report

This section gives the results of a calculation of upper and lower peak voltages on a net as a result of its aggressors. This list is sorted according to the peak noise voltage value. Only nets for which the peak noise voltage is above the threshold given by the ctknoisemin configuration variable are reported.

The syntax of this section is as follows:

BeginNoise
  DW|UP <signal> <mod ovr> <max ovr> <real ovr> \\
                 <mod und> <max und> <real und>
  |
  DW|UP <signal> <mod ovr> <max ovr> <real ovr> \\
                 <mod und> <max und> <real und>
EndNoise

For each state (UP or DOWN) of a signal, the crosstalk engine gives the peak noise voltage (<max ovr> and <max und>) calculated with all aggressors considered active, and the "real" noise voltage (<real ovr> and <real und>) calculated considering possible switching configurations of aggressors. <mod ovr> and <mod und> are the electrical model used to evaluate peak noise voltage.

Currently, the noise voltage on the net is evaluated by replacing the net driver by a single equivalent constant-valued resistor. This value is either determined from the transistor netlist (model SCR) or, if this is not possible, defined by the ctknoisedefaultresi configuration variable (model CC). Both overshoot and undershoot values are calculated for each signal state.

2. 6. CTX - Annotated Perfmodule Format

The CTX file (suffix .ctx) is an ASCII text file containing all the delays calculated with crosstalk effects of a complete design hierarchy. This file is associated with all of the original detailed perfmodule files describing the hierarchy. It is intended to be viewed using the timing browser Xtas. This file contains four parts:

2. 6. 1. General Header

The CTX file header is the same as the corresponding perfmodule file of the top level of the design:

H <tool> <vers> <name> <techno> 
<techno_vers> <inslope> <outcapa> <hierarchy_level> 
(<day> <month> <year> <hour> <minute> 
<second>);

2. 6. 2. Top Level Delays

Part of this file contains all the delays of the top level.

M <subcircuit name> (
  D <line index> ( 
     ((MAX <delay> <slope>))
     ((MIN <delay> <slope>))
    )
  |
  |
  D <line index> ( 
     ((MAX <delay> <slope>))
     ((MIN <delay> <slope>))
    )
)

The <line index> value is the index of the corresponding line in the detailed timing perfmodule.

2. 6. 3. Instance delays

This section gives all delays for all instances.

I <instance name> (
  D <line index> ( 
     ((MAX <delay> <slope>))
     ((MIN <delay> <slope>))
    )
  |      |
  |      |
  D <line index> ( 
     ((MAX <delay> <slope>))
     ((MIN <delay> <slope>))
    )
)
|
|
I <instance name> (
  D <line index> ( 
     ((MAX <delay> <slope>))
     ((MIN <delay> <slope>))
    )
  |      |
  |      |
  D <line index> ( 
     ((MAX <delay> <slope>))
     ((MIN <delay> <slope>))
    )
)

For each instance, the <line index> value is the index of the corresponding line in the detailed timing perfmodule.

2. 6. 4. The End of File

The end of the CTK file is given by the G; article.