RE: [openrisc] Cell not translated

["Richard Herveille" <richard@asics.ws>]

> 
> Richard: Have you been using Xilinx tools for synthesis of 
> OR1200? If so, 
> which libraries have you been using for the RAM blocks? I have 
> confirmed that tri0 net is unsupported in xst.
> 
> Regards,
> Sandeep.

This didn't occur to me before, but it might be that you're looking in
the wrong direction.

'tri0' is a verilog reserved keyword. It's a tri-net with a pull-down
resistor model.

Maybe that provides a clue?

Richard

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