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[cvs-checkins] pci/rtl/verilog pci_target32_interface.v pci_t ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] pci/rtl/verilog pci_target32_interface.v pci_t ...
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Thu, 21 Aug 2003 22:55:32 +0200
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	tadejm	03/08/21 22:55:32

Modified files:
	rtl/verilog    : pci_target32_interface.v pci_target_unit.v 

Log message:
	Corrected bug when writing to FIFO (now it is registered).

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