[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] can/ ench/verilog/can_testbench.v im/rtl_sim/b ...

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/08/20 12:03:57

Modified files:
	bench/verilog  : can_testbench.v 
	sim/rtl_sim/bin: memory_file_list 
	sim/rtl_sim/run: run_sim.scr 

Log message:
	Artisan RAMs added.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml