[cvs-checkins] pci/ ench/verilog/pci_behaviorial_target.v enc ...

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	03/08/03 20:05:10

Modified files:
	bench/verilog  : pci_behaviorial_target.v pci_blue_options.vh 
	                 pci_bus_monitor.v pci_testbench_defines.v 
	                 system.v wb_bus_mon.v wb_master32.v 
	                 wb_master_behavioral.v 
	rtl/verilog    : pci_bridge32.v pci_user_constants.v 
	                 pci_wb_slave.v top.v 
	sim/rtl_sim/bin: rtl_file_list.lst 
	sim/rtl_sim/run: ncvlog.args run_pci_sim_regr.scr 

Log message:
	Added limited WISHBONE B3 support for WISHBONE Slave Unit.
	Doesn't support full speed bursts yet.

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