Re: [fpu] FRem

[Jamil Khatib <jamilkhatib75@yahoo.com>]

> > What I am not sure about is if I add mod operator
> to
> > the fdiv code what is going to happen after
> synthesis
> > (i.e. which approach will be used )
> 
> Depends what synthesis tool you use and what
> libraries
> come with it. Synopsys design compiler usually comes
> with a Design Ware library. I don't know if it has
> a mod operator or not, and if it does how it is
> implemented.
> 
In fact I do not have any synthesis tool for verilog
that why I asked for help

> I don't see the use of this, as you can not provide
> the
> result of a fdiv and the remainder at the same time,
> without
> modifying the architecture of the FPU.

yes you are right I have to implement the div and rem
functions, but my suggestion is to use is as in the
add/sub core


> 
> Why don't you get the basic function working first,
> and then
> try to add additional features.

The divider is working almost fine but I have the
followings missing:
1. overflow, underflow, and inexact exceptions
2. Rounding 

I think these should be the same as in all blocks so I
am waiting for your approach so as not to have
different roundings.

> 
> > anyhow what is the mod or rem operator in verilog?
> 
> Same as it is in any other programming language: '%'
> 
> > Regards
> > Jamil Khatib
> > 
> 
> rudi
> 


__________________________________________________
Do You Yahoo!?
Yahoo! Mail - Free email you can access from anywhere!
http://mail.yahoo.com/