Re: [fpu] fdiv problem

[Rudolf Usselmann <rudi@asics.ws>]

on 8/28/00 13:18, Jamil Khatib at jamilkhatib75@yahoo.com wrote:
> The problem with Rudi's pattern generator that it does
> not give numbers that we can understand (only for the
> test bench)
> what I want is a verification software at least to
> generate the patterns, perform the operation and
> display the results of the sofwtare and the fp
> execution unit (may be later we can also make
> automatic checking)

The test pattern generator generates proper floating point
numbers and results. It appears that you don't understand how
to integrate it into a test bench and how to write a test
bench. You need to learn to look at floating point numbers in
their native IEEE representation and understand what it all
means.

> Exceptions also are very important to check so they
> must be predicted.

Again, you are totally clueless. Have you actually looked
at the pattern generator ??? It does all of that and more.

> I need this software as soon as possible. If you do
> not have time I can work on that part if no one is
> working on it now

Yea, go ahead write your own stuff ...

Are you going to have working (tested) code in a week so
I can integrate it with the rest by mid September ? That's
when Damjan needs the FPU for tape out.

> Anyhow I need the test bench and the pattern reader so
> as to interface it to the divider.

I have emailed out some examples some time ago.

> Jamil Khatib

rudi