[fpu] fdiv verilog code

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi,

I attached my verilog code.
It still have some bugs like, overflow and under flow
exceptions, and rounding.

In fact the code does not work and I do not know why
because I do not have that much experiance in verilog.
During simulation it stops over the case statment and
acts as if non of the cases is matched and no
assinments are done to the output.

Could you please let me know where is the problem and
how to fix it.

Can you simulate it if it is possible and give me also
the timing results

One final question: in case of divide by zero should I
also rise the invalid exception?


Regards
Jamil Khatib


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fdiv.v