RE: [fpu] FPU operations

["Rudolf Usselmann" <russelmann@hotmail.com>]

>From: owner-fpu@opencores.org [mailto:owner-fpu@opencores.org]On Behalf
>Of Jamil Khatib
>
>
>Hi all,
>It is nice to get all these emails, your discussions
>have answered most of my questions.
>
>I have few comments:
>
>1. When I said that different operands may need
>different clocks to get the result I meant that
>special numbers may produce results faster than normal
>ones, because they do not need to be addede.......
>This apeer in my first suggested flow chart but I
>fixed it later. I am going to pass all numbers onm the
>same logic and finally I'll decided which one to pass.
>The new flow chart is located under fpu site at
>./fpu/add2_flow.ps

Right, all numbers should take the same amount of time.

>
>2. When I asked about contention on the result bus, it
>was another way to ask about different execution
>speeds of the FPU units. For example:
>ADDER needs 3 clks
>MULTIPLIER needs 4 clks
>and a mul instruction is issued on clock before add
>inst what will happen on the result. Both add and mul
>instructions have to write to the result. as I know
>there should be a method to stall the adder, how can
>you manage this kind of operations?

That's why I was saying to Damjan we need to stretch the
adder. All basic FP units that share a result bus, must
take the same amount of time to execute.

>3. OK about the comparison status signals we have also
>to add zero status but all these comparisons have to
>execute in parallel with all instructions.

Right, there are also other issues to be resolved.
I don't have the time right now to deal with that. This
should be easy and we can resolve it at a later point.


>4. My adder is almost ready and located in the CVS. it
>supports Special numbers handling (inf & NaN) and
>generates Invalid exception. but still it have to
>generate overflow and underflow.

So now we have two implementations ?
I don't understand why you not work on something that is
not being worked on, like the divider ???
Fine, I will discontinue working on mine. Damjan, please
get them removed from opencores web site ....

>5. Initial synthesis showed that the 32 bit Add
>(represented by + operator) which is performed on a
>single pipeline is located in the critical path. still
>I have to investigate more.

Can you provide more information here ? What are you using
for synthesis, and what technology are you synthesizing to ?


>6. I think we should provide SNAN when NAN is one of
>the comparison operands but also we should produce
>false for this kind of operation. This is even if the
>standard does not require it but it will give the
>software more control.

NO ! I think we should follow the rules described in
IEEE-754, or this entire project will become worthless,
because fpu is non-standard.


>7. Since we are working on HDL coding why do not we
>agree on the same structure and code it and have one
>in VHDL and one in verilog. ( as I remmber OR1K was
>written in VHDL is there any plans for writing it in
>verilog?)

I remember reading something from Damjan that he is writing
everything in Verilog now. I do not know VHDL well enough
to code in it, and do not have any desire to learn it nor
to code in it.
Why don't you agree with yourself on the some structure etc.,
and let the rest of us do what we do best - designing hardware.

>
>8. I am going to modify the flow charts, block
>diagrams and the design document soon according to
>these discussions
>
>
>Regards
>Jamil Khatib

rudi
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