Re: [fpu] Architecture

["Damjan Lampret" <damjan.lampret@arnes.si>]

I was away for the last six days so I'll go in discussion with you from now
on.

I think x86 type of FPU is not what we want to do. Our is not like
"coprocessor" but it is a functional (sometimes a.k.a execution) unit. I
think you both agreed on this and I like it too. So we should make FPU that
fits in parallel with load/store unit, integer unit etc. All insn
decode/issueing is done by the common insn decoder/issue stage. So our CPU
has LSU, IU, FPU (and perhaps some other units). At least FPU is optional.
The first question that pops up is do we use pairs of 32 bit registers to do
double precision (I am not talking about internal represention that can be
80 or even more bits)? In this case would would need 4 read ports on
register file. Perhaps FPU should be scalable so that you can either do both
single and double or just single precision since at least implementations
that are die area sensitive won't use double precision.

regards, Damjan

PS I like PPC architecture manual and description of FP operands and MPC7xx
manual and description of FPU (it doesn't go into microarchitecture details
of course).

----- Original Message -----
From: Jamil Khatib <jamilkhatib75@yahoo.com>
To: <fpu@opencores.org>
Sent: Sunday, April 23, 2000 8:23 AM
Subject: Re: [fpu] Architecture


[cut]
> After reading the 387SX coprocessor and IA64 manual, I have some questions
and
> comments:
>
[cut]