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[usb] Re: usb-digest V1 #254

To: "usb@opencores.org" <usb@opencores.org>
Subject: [usb] Re: usb-digest V1 #254
From: "henry_xb" <xxiaobin@263.net>
Date: Fri, 16 May 2003 9:12:15 +0800
Reply-To: usb@opencores.org
Sender: owner-usb@opencores.org
Hi friend:

 I'd like to discuss the topic about DPLL. And there is anybody interest it?
			
Best Regard
 
				 
　　　　　　　　henry_xb
　　　　　　　　xxiaobin@263.net
　　　　　　　　　　2003-05-16


======= 2003-05-15 17:20:00 in Your email：=======

> usb@opencores.org	 usb-digest V1 #254
>
>
>----------------------------------------------------------------------
>From: mdennis97@hotmail.com
>Date: Thu, 15 May 2003 07:43:27 -0100
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>2003
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>Date: Thu, 15 May 2003 07:43:27 -0100
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>Message-Id: <200305150843.h4F8hRjI018291@www.opencores.org>
>Subject: Re: [usb] Please help with a USB DPLL
>To: usb@opencores.org
>From: mdennis97@hotmail.com
>Sender: owner-usb@opencores.org
>Precedence: bulk
>Reply-To: usb@opencores.org
>
>Thanks, Mr. rudi:
>  The usb phy you have contributed uses 48mhz as its clock.Taking into 
>account the host side applications, host controller may signal in low 
>speed and full speed. In this condition, I don't know if a single phy can 
>deal with those tasks. If it does, when working at low speed, can we 
>connect the clk signal of the phy to a 6mhz clock which may be derived 
>from the 48mhz?
>  Furthermore, after having completed the low speed transaction, the 
>phy clock should be switched back to 48mhz. Does this suppositon work?
>
>Regards
>
>Dennis
>
>----- Original Message ----- 
>From: Rudolf Usselmann <rudi@a... > 
>To: usb@o...  
>Date: 13 May 2003 13:01:41 +0700 
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL 
>
>> 
>> 
>> On Tue, 2003-05-13 at 15:19, mdennis97@h...  wrote: 
>> > hi, Mr. rudi: 
>> > 
>> >   As far as I know, your dpll is based on full speed. If there 
>> is a low 
>> > speed device to be applied, how to modify this logic core?That 
>> is, for 
>> > the host controller, can we use your dpll for a reference? 
>> >   Maybe it's a difficult project. 
>> > 
>> > Regards 
>> > 
>> > Dennis 
>> 
>> Just modify it to generate 1.5 Mhz clock enables - use 
>> every 8th one from 12 Mhz ... 
>> Or modify the FSM accordingly ... should be trivial 
>> 
>> 
>> 
>> rudi 
>> ------------------------------------------------------- 
>> www.asics.ws  -- Solutions for your ASIC/FPGA needs --- 
>> ---------------- FPGAs * Full Custom ICs * IP Cores --- 
>> * * * FREE IP Cores  --> http://www.asics.ws/ <-- * * * 
>> 
>--
>To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>From: Rudolf Usselmann <rudi@asics.ws>
>Date: 15 May 2003 13:20:38 +0700
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>On Thu, 2003-05-15 at 15:43, mdennis97@hotmail.com wrote:
>> Thanks, Mr. rudi:
>>   The usb phy you have contributed uses 48mhz as its clock.Taking into 
>> account the host side applications, host controller may signal in low 
>> speed and full speed. In this condition, I don't know if a single phy can 
>> deal with those tasks. If it does, when working at low speed, can we 
>> connect the clk signal of the phy to a 6mhz clock which may be derived 
>> from the 48mhz?
>>   Furthermore, after having completed the low speed transaction, the 
>> phy clock should be switched back to 48mhz. Does this suppositon work?
>> 
>> Regards
>> 
>> Dennis
>
>Well, this phy was designed with full speed in mind only.
>
>Switching clocks is always a bad idea. Take a closer look
>how the DPLL works and how the actual 12Mhz clock is generated.
>If I remember correctly, everything runs at 48Mhz all the
>time, and I use clock enable to advance the rx and tx logic
>at a 1/4 speed 9e.g. 12 Mhz). My guess would be that it
>would be a much cleaner solution to modify the DPLL to
>support LS speed mode.
>
>If you do make these modifications, please submit your
>work to OpenCores as well.
>
>rudi
>-------------------------------------------------------
>www.asics.ws  -- Solutions for your ASIC/FPGA needs ---
>---------------- FPGAs * Full Custom ICs * IP Cores ---
>* * * FREE IP Cores  --> http://www.asics.ws/ <-- * * *
>
>
>
>--
>To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>From: mdennis97@hotmail.com
>Date: Thu, 15 May 2003 10:44:29 -0100
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>2003
>Received: (from majordomo@localhost)
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>Date: Thu, 15 May 2003 10:44:29 -0100
>X-Virus: 6
>Message-Id: <200305151144.h4FBiTmH002867@www.opencores.org>
>Subject: Re: [usb] Please help with a USB DPLL
>To: usb@opencores.org
>From: mdennis97@hotmail.com
>Sender: owner-usb@opencores.org
>Precedence: bulk
>Reply-To: usb@opencores.org
>
>ok. I will try. And your advice will be the best help.
>
>----- Original Message ----- 
>From: Rudolf Usselmann <rudi@a... > 
>To: usb@o...  
>Date: 15 May 2003 13:20:38 +0700 
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL 
>
>> 
>> 
>> On Thu, 2003-05-15 at 15:43, mdennis97@h...  wrote: 
>> > Thanks, Mr. rudi: 
>> >   The usb phy you have contributed uses 48mhz as its 
>> clock.Taking into 
>> > account the host side applications, host controller may signal 
>> in low 
>> > speed and full speed. In this condition, I don't know if a 
>> single phy can 
>> > deal with those tasks. If it does, when working at low speed, 
>> can we 
>> > connect the clk signal of the phy to a 6mhz clock which may be 
>> derived 
>> > from the 48mhz? 
>> >   Furthermore, after having completed the low speed 
>> transaction, the 
>> > phy clock should be switched back to 48mhz. Does this 
>> suppositon work? 
>> > 
>> > Regards 
>> > 
>> > Dennis 
>> 
>> Well, this phy was designed with full speed in mind only. 
>> 
>> Switching clocks is always a bad idea. Take a closer look 
>> how the DPLL works and how the actual 12Mhz clock is generated. 
>> If I remember correctly, everything runs at 48Mhz all the 
>> time, and I use clock enable to advance the rx and tx logic 
>> at a 1/4 speed 9e.g. 12 Mhz). My guess would be that it 
>> would be a much cleaner solution to modify the DPLL to 
>> support LS speed mode. 
>> 
>> If you do make these modifications, please submit your 
>> work to OpenCores as well. 
>> 
>> rudi 
>> ------------------------------------------------------- 
>> www.asics.ws  -- Solutions for your ASIC/FPGA needs --- 
>> ---------------- FPGAs * Full Custom ICs * IP Cores --- 
>> * * * FREE IP Cores  --> http://www.asics.ws/ <-- * * * 
>> 
>--
>To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>From: mdennis97@hotmail.com
>Date: Thu, 15 May 2003 16:50:01 -0100
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>2003
>Received: (from majordomo@localhost)
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>Date: Thu, 15 May 2003 16:50:01 -0100
>X-Virus: 6
>Message-Id: <200305151750.h4FHo1se029440@www.opencores.org>
>Subject: Re: [usb] Please help with a USB DPLL
>To: usb@opencores.org
>From: mdennis97@hotmail.com
>Sender: owner-usb@opencores.org
>Precedence: bulk
>Reply-To: usb@opencores.org
>
>----- Original Message ----- 
>From: Rudolf Usselmann <rudi@a... > 
>To: usb@o...  
>Date: 15 May 2003 13:20:38 +0700 
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL 
>
>> 
>> 
>> On Thu, 2003-05-15 at 15:43, mdennis97@h...  wrote: 
>> > Thanks, Mr. rudi: 
>> >   The usb phy you have contributed uses 48mhz as its 
>> clock.Taking into 
>> > account the host side applications, host controller may signal 
>> in low 
>> > speed and full speed. In this condition, I don't know if a 
>> single phy can 
>> > deal with those tasks. If it does, when working at low speed, 
>> can we 
>> > connect the clk signal of the phy to a 6mhz clock which may be 
>> derived 
>> > from the 48mhz? 
>> >   Furthermore, after having completed the low speed 
>> transaction, the 
>> > phy clock should be switched back to 48mhz. Does this 
>> suppositon work? 
>> > 
>> > Regards 
>> > 
>> > Dennis 
>> 
>> Well, this phy was designed with full speed in mind only. 
>> 
>> Switching clocks is always a bad idea. Take a closer look 
>> how the DPLL works and how the actual 12Mhz clock is generated. 
>> If I remember correctly, everything runs at 48Mhz all the 
>> time, and I use clock enable to advance the rx and tx logic 
>> at a 1/4 speed 9e.g. 12 Mhz). 
>
>Why not use a static 12Mhz clock for the transmit module?For many 
>applications, 12Mhz clock is always available.
>
>My guess would be that it 
>> would be a much cleaner solution to modify the DPLL to 
>> support LS speed mode. 
>> 
>> If you do make these modifications, please submit your 
>> work to OpenCores as well. 
>> 
>> rudi 
>> ------------------------------------------------------- 
>> www.asics.ws  -- Solutions for your ASIC/FPGA needs --- 
>> ---------------- FPGAs * Full Custom ICs * IP Cores --- 
>> * * * FREE IP Cores  --> http://www.asics.ws/ <-- * * * 
>> 
>--
>To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>End of usb-digest V1 #254
>-
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