Re: [usb] Please help with a USB DPLL

[mdennis97@hotmail.com]

hi, Mr. rudi:

  As far as I know, your dpll is based on full speed. If there is a low 
speed device to be applied, how to modify this logic core?That is, for 
the host controller, can we use your dpll for a reference?
  Maybe it's a difficult project.

Regards

Dennis

----- Original Message ----- 
From: Rudolf Usselmann <rudi@a... > 
To: usb@o...  
Date: 13 May 2003 01:04:34 +0700 
Subject: Re: [usb] Please help with a USB DPLL 

> 
> 
> 
> 'a' and 'b' are just two different sync stages the state 
> machine can be in. The resulting clock from either stage 
> is 12 Mhz. I personally find the example in siewp.pdf way 
> to over-engineered. I wrote a USB 1.1 PHY with a simple 4 
> stage state machine, and have tested it in hardware. It 
> appears to work just fine. I have never understood the extra 
> complexity in the siewp.pdf. 
> 
> See OC for the PHY ... 
> 
> Regards, 
> rudi 
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