Re: [usb] DPLL in USB2.0

[Phlei@yahoo.com]

Hi All,
As far as I know you don't need the 4x clock, the HS uses four phases 
from the APLL and then evaluate the transition between phases, it 
works the same as 4X DPLL. you have zero degree, ninty degree,180 
degree and 270 degree, all four phases. The VCO in the APLL has equal 
four sections and you bring out each section outputs. It can be done 
with DPLL too, the delay chain will be four equal sections and every time 
you increment four tips or decrement four tips at a time when it is 
locked, you know the delay chain output from the up down counter.

-Phil

----- Original Message ----- 
From: Rudolf Usselmann <rudi@a... > 
To: usb@o...  
Date: 24 Feb 2003 00:22:53 +0700 
Subject: Re: [usb] DPLL in USB2.0 

> 
> 
> On Wed, 2003-02-19 at 10:39, henry_xb wrote: 
> > Hi friends！ 
> > 
> > The Dpll in Usb2.0 use a statemachine to detract the data and 
> clock ,Can tell me how it works? 
> 
> Really ?!  You should tell us how it works ! 
> Or search the usb.org site yourself to find the white 
> paper that explains it ... 
> 
> Lets, see, data rate about 480 Mbit/s, 4x oversampling (not sure 
> if that meets USB 2.0, but just for this argument ...), would 
> mean 1920MHz clock for your state machine ! 
> 
> I guess full custom circuit in 0.13u ? 
> 
> Wouldn't an Analog PLL be a better choice ? 
> 
> I think you know of some secrets we don't know ! :*) 
> 
> > 		 
> > Best Regard 
> > 
> > 				 
> > 　　　　　　　　henry_xb 
> > 　　　　　　　　xxiaobin@2...  
> > 　　　　　　　　　　2003-02-19 
> > 
> 
> 
> Cheers ! 
> rudi 
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