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RE: [usb] RE: usb
In my analogy, the compiler could be the synthesizer of the work we are
doing.
There are many software products out there that use a *portion* of GPL'd
software that interfaces with their proprietary software. They do not need
to release the specs or source or whatever for the proprietary portion as
long as it is not a modified GPL'd piece of code. A separate object file
made independent of the GPL'd code, but that can communicate with it. I
think Tivo is a good example of this.
The source codes I was speaking of before were the VHDL or Verilog versions
of a core.
-----Original Message-----
From: Joe Zott [mailto:jaz@itvc.com]
Sent: Wednesday, March 08, 2000 11:36 AM
To: usb@opencores.org
Subject: RE: [usb] RE: usb
At 10:48 AM 3/8/00 -0500, you wrote:
>I think the GPL is suitable for certain source codes like Verilog, VHDL, C
&
>C++ as far as simulation goes.
Actually no. For example, if you were integrating models of commercial
items, e.g., memory, you might not have the right to release that portion
of your overall simulation model.
---my reply:
---
Also, the GPL is very specific with the word "software". I suspect that a
good lawyer would be able to show that the license doesn't apply at all to
a Verilog/VHDL design used for anything but simulation.
---my reply:
I didn't mean to imply using an unmodified GPL, but I think it could easily
be adapted. And exactly how is it that VHDL is not software?
---
>source code, or a derivative of that code, that the source code be made
>readily available to anyone who uses that physical core.
What is the source code in this context. GPL and related licenses are clear
that make files needed to generate the binary must be released. Do the
synthesis scripts need to be released? How much else?
---my reply:
The VHDL is the source code I was referring to (or Verilog).
I'd like for you to prove that anyone needs a make file to generate a
binary. They are a convenience, and in theory, though it may take years :),
one could generate a binary with out a make file. Certainly on less complex
projects.
If you want to release synthesis scripts, that's fine. if you don't that is
fine too.
What if you release synthesis scripts that only work with a commercial
synthesizer?
I am not a lawyer. So I may be incorrect in saying this, but AFAIK one does
*not* need to release the source code of a compiler they use to compile
something that is GPL'd.
---
>use something like Mosis if we were to use a fab, so fab specs aren't going
>to be a big secret (AFAIK).
Not true. I use MOSIS brokered fabs and sign non-disclosure licenses to
gain access to the specs for the contracted fabs. Also, if you are not
using public domain cell libraries then there is an issue related to their
use.
--my reply:
I stand corrected. I've never done anything with Mosis.
As far as public domain cells, and use issues, that has nothing to do with
the source code. That is an implementation problem, and not necessarily our
problem. We aren't releasing silicon (necessarily).
---
>I was under the impression that most of this
>stuff was to be synthesized on an FPGA (virtex?).
With high end Virtex FPGAs being over a thousand dollars many of the cores
that are being proposed will be very expensive implemented that way. If we
want to only be designing stuff for simulation or those few people who can
afford those costs that is fine, but I thought the intent was to create an
open environment for sharing intellectual property.
---my reply:
And Mosis is cheaper? (I am asking seriously, not sarcasm) What are some
other options?
---
>Is it a concern if somebody synthesizes a core from the HGPL'd code with
>secret fab specs that allow higher MHz? This seems to me to be analogous
to
>writing one's own super special highly optimized compiler to compile GPL'd
>code that will run faster than the rest. If one were to write this
compiler
>on their own, they would be under no obligation to share that compiler
code.
>If they distributed their highly optimized binary, they would only be
>obligated to make available the source to that binary.
An excellent point, but what is "source" for a hardware design? If I make
changes in the design to improve the design for a synthesizer/cell
library/layout that you don't have what is my responsibility to release
such information?
---my reply:
The way I see it, VHDL (can you tell I have a preference? :) or Verilog are
the source. To me, synthesis and the act of synthesis are just like
compiling the code. I see your point from above about synthesis scripts,
but that seems like a trivial matter to correct, if it is a concern at all.
I see no obligations to release anything regarding a library or cell.
Are there not open source projects that use Motif?
---
>The EFF might be interested and able to help with the modification to the
>GPL.
>Does this make sense?
Absolutely. My major concern is that people are volunteering their time for
a certain objective, but without the necessary legal structure in place
then we need to be very careful that they are getting what they expected. I
attached a post I made some time ago about this issue.
Joe
---my reply:
yes, that is a very good point...that right now any code posted to the cvs
is pretty much public domain, take it if you want it and do what you will.
Which is probably why you won't find too much VHDL or whatnot in there yet.
I've just read the post below. It seems that I think that a license
covering the source (VHDL files) is enough, whereas you would like to go
further and cover the implementation.
Perhaps multiple licenses are in order?
--Scott
p.s. I apologize for the goofiness of the organization of my replies... I
don't have outlook configured to put the ">" in front of old text...
---
-------------
While I generally agree that we should be using a GNU GPL, my concern is
that any license agreement used for open IP hardware provide for use of the
cores in ASICs. In order to do so we need to permit:
* Necessary changes to deal with proprietary tools, cell libraries, etc.
Some of these changes may be confidential.
* Ability to integrated cores with proprietary cores.
* Ability to modify core as necessary to integrate with proprietary cores.
Even the interface to some cores is confidential.
* Ability to modify design to meet the specific requirements of a project.
I believe that it is reasonable to require that these changes to be made
publicly available even if they would represent a development branch that
active open source developers would not be interested in.
The open IP hardware community should expect and require:
* that improvements to the general good be shared with everyone
* that users contribute design changes to increase the usability and
applicability of the core
* that documentation, supporting tools, and verification results be freely
shared
I am not a lawyer (but forgive me for doing what people normally do after
saying that and make legal points)
1. The unmodified GNU GENERAL PUBLIC LICENSE really only applies to
software.
2. Translating the GPL from software to hardware I believe would require
the ASIC developer to release the masks for any design incorporating a GPL
core. That means that they couldn't use proprietary cores or cells in their
design. (Does anyone have an open-IP 0.35um cell library in the fab of my
choice that I can use with my copy of Synopsys Design Compiler?) For our
custom hardware design projects fabs require us to sign non-disclosure
agreements. I don't know that a completely open IP cell library is even
possible. Strict compliance with GPL seems to imply that you can't use the
IP for ASICs.
3. The GNU Library General Public License seems like a better model as it
provides for combining proprietary and open stuff. It also was written for
software and not hardware though.
4. It is not clear to me the provisions of this license (ref. para. 5 & 6)
would be interpreted for a hardware development.
5. Some provisions in the LGPL do appear to present problems to the ASIC
developer, e.g., "For an executable, the required form of the "work that
uses the Library" must include any data and utility programs needed for
reproducing the executable from it." Does that mean that I need to provide
a copy of Synopsys Design Compiler ($200K+ to anyone who asks me to buy a
copy for them)?
Regards,
Joe
VP Engineering, The iTv Corporation
jaz@itvc.com