Re: [pci] SEL_I signals

[mv <mxv@yahoo.com>]

Marco,

For 32 bit transfers:

SEL_I[3:0]=4b'1111; 
ADDR[1:0]=2'b00;

See wishbone spec for more details on SEL usage.

Regards,
Manoj

--- Marco Buffa <marcobuffa@lombardiacom.it> wrote:
> Hi,
> I'm implementing a wishbone master unit to connect
> to wb_slave unit of 
> the pci bridge. I need to transfer only 32bit data,
> so I would like to 
> hardwire SEL_I signals of slave unit.
> 
> Reading the PCI IP Core Specification I find (page
> 21 fo pdf document) 
> that if I have my image mapped in to memory (and so
> is), I need to use 
> only addresses with ADDR_O(1:0)=0x00, so SEL_O(0)
> line of my master unit 
> must be '1' and the others doesn't care.
> 
> It's right?
> 
> Thank's.
> -- 
> 
> Marco Buffa (Politecnico di Milano, Italy)
>  
> "Qui se accendessero le luci e riabbassassero le
> luci 
> ci troverebbero tutti in piedi con gli occhi aperti,
> qui" 
> (Ivano Fossati, "Sigonella")
> 
> 
> --
> To unsubscribe from pci mailing list please visit
http://www.opencores.org/mailinglists.shtml


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