Re: [pci] Master capability

["Gvozden Marinkovic" <mgvozden@eunet.yu>]

PCI core is a bridge. You have to write base (memory) physical address to one of
the core registers, and the core will match (translate) WISHBONE address (that
your
master generates) to PCI address (first n bits, depends on configuration).

Sincerely,

Gvozden


----- Original Message -----
From: "Marco Buffa" <marcobuffa@lombardiacom.it>
To: <pci@opencores.org>
Sent: Tuesday, July 15, 2003 6:40 PM
Subject: [pci] Master capability


> Good morning.
>
>
> In the /proc filesystem I read that the pci core (guest) is master capable.
> How can I grant the mastership on the bus?
> I suppose I need to use the REQ/GNT PCI signals, but I can't understand
> how to control them.
>
> Thank's a lot.
> --
> Marco Buffa (Politecnico di Milano, Italy)
>
> "Qui se accendessero le luci e riabbassassero le luci
> ci troverebbero tutti in piedi con gli occhi aperti, qui"
> (Ivano Fossati, "Sigonella")
>
> --
> To unsubscribe from pci mailing list please visit
http://www.opencores.org/mailinglists.shtml
>




--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml