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[pci] Patch: Don't concatenate with unknown length inwb_bus_mon.v
Hallo,
trying to get the test bensch to compile with Icarus Iverilog, Iverilog
choked on the concatenation {1'b1, (ADDR_O + `WB_SEL_WIDTH)}. Stephen
Williams, the author of iverilog, told be that Icarus doesn't make
assumptions on the length of the define, and so the warning was right.
Appended patch should fix the problem.
Bye
PS: Iverilog still fails in a later place.
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
--- pci.orig/bench/verilog/wb_bus_mon.v 2002-08-13 13:03:51.000000000 +0200
+++ pci//bench/verilog/wb_bus_mon.v 2003-07-05 17:43:40.000000000 +0200
@@ -329,7 +329,7 @@
if (STB_O && ACK_I)
begin
if (address[`WB_ADDR_WIDTH] == 1'b0)
- address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
+ address <= {1'b1, (ADDR_O + 1'b1<<`WB_SEL_WIDTH-1)} ;
else
begin
if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
@@ -338,7 +338,7 @@
$fdisplay(log_file_desc, "Consecutive address burst address incrementing incorrect") ;
end
else
- address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
+ address <= {1'b1, (ADDR_O + 1'b1<<`WB_SEL_WIDTH-1)} ;
end
end
end
--
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