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[pci] PCI bridge as Guest



Good day!

I'd like to ask and clarify some things about the pci bridge core. My
question has something to do with the wishbone interface which I'm not
familiar with, so any help is greatly appreciated.

If I wanted to implement the core as a guest with the connection of a
device on the wishbone bus, which parts of the pci bridge core are used?


Is the wishbone slave module as well as its FIFOs still in use? 

Let's say data is requested from the pci host to the device(which is
connected to the wishbone bus), then data transfers are passing through
the pci bus then to the pci target module then to the wishbone master
module and eventually to the device connected to the wishbone bus. In
this case, what is the role of the wishbone slave module that is
connected to pci master module?

I might be misunderstanding something so please correct me if I'm wrong.

Thank you very much for any help!

Regards,
Radwin Zagala

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