Re: [pci] ucf

[Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>]

>>>>> "Haiko" == Haiko Morgenstern <haiko.morgenstern@izm.fraunhofer.de> writes:

    Haiko> Hello, we want to reproduce the vga-application and are not 100%
    Haiko> shure how to setup the project. this are the steps we already
    Haiko> done (we use ISE5.1):

    Haiko> 1. setup project settings (SpartanII 200k; BGA456; Speedgrade 6;
    Haiko> Verilog) 2. added all pci-brigde source files and after this we
    Haiko> added all appication files (overwrite all duplicate ones)
    Haiko> 3. modification of pci_user_constans.v to use Xilix Block RAM
    Haiko> `define PCI_XILINX_RAMB4 `define WB_XILINX_RAMB4 //`define
    Haiko> PCI_XILINX_DIST_RAM //`define WB_XILINX_DIST_RAM 4. after this i
    Haiko> clicked at the synthesize button and got a lot warnings
    Haiko> (redefinition of signal XXX), but the process was finished
    Haiko> without errors

    Haiko> is this procedure correct and can i ignore the warnings? 

When synthezising with webpack5.2, I got a lot of warnings too. The VGA
module ran despite of these warnings.

    Haiko> can
    Haiko> someone provide a ucf-file for the opencore pci-brigde that runs
    Haiko> on the memec-development board with spartan II (200k)?

Look into apps/crt/syn/webpack. For the UCF file, you need to adapt for
where you put he R2R DAC. The npl file only works with 5.2 and the pathes
need to be adapted.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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