Re: [pci] parity errors when simulation

["Miha Dolenc" <mihad@opencores.org>]

This is OK.
The testbench is intentionally causing this errors, to test the
functionality of parity generation and checking in the PCI Bridge.

Regards,
Miha Dolenc

----- Original Message -----
From: <random_user@163.com>
To: <pci@opencores.org>
Sent: Monday, August 12, 2002 12:33 PM
Subject: [pci] parity errors when simulation


> When I tried to simulate the PCI core,the log file of VCS tell me that
> there are some parity errors occured.
> 1.Invalid write data parity error
> 2.Undetected read data parity error
>
> I want to know whether I am simulating the core in a wrong way.
> Any help will be appreciated!
>
> regards,
> wangc
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