Re: [pci] PCI bus in Quartus II 2.0??????

[cfk <cfk@pacbell.net>]

The undef issues, just to document them are common to both ISE and WebPack
and they seem to be quite minor. They are:

1) wb_addr_mux.v line 165 `undef DECO_INCLUDE
2) wb_slave.v line 1033 `undef DO_OUT_MUX
3) pci_tprm.v line 308, `undef RAM_SELECTED
4) wb_tpram.v line 310 `undef RAM_SELECTED

I find that the core compiles just fine with these four statements commented
out, and I am using it in a VirtexE FPGA with ISE.
Charles

----- Original Message -----
From: "Miha Dolenc" <mihad@opencores.org>
To: <pci@opencores.org>
Sent: Friday, July 26, 2002 12:16 AM
Subject: Re: [pci] PCI bus in Quartus II 2.0??????


> Hi!
>
> I hear about this problem for the first time now. As far as I know, people
> have successfully compiled the core with:
> - synopsys fpga express
> - leonardo
> - synplify pro
> - xilinx ISE
> - xilinx web pack (some problems here with `undef directive)
>
> I don't remember anyone trying to do it with Quartus.
>
> I would suggest you contact Altera support about this problem.
> Maybe defparam directive should be used for Quartus instead of parameter
> values in module instantiation.
>
> Regards,
> Miha Dolenc
>
> ----- Original Message -----
> From: <klm681@mail.usask.ca>
> To: <pci@opencores.org>
> Sent: Thursday, July 25, 2002 9:11 PM
> Subject: [pci] PCI bus in Quartus II 2.0??????
>
>
> > Has anyone compiled the PCI bus IP core using Quartus II 2.0 software
> > from Altera?  I tried, but I get this error message :"Unsupported
Verilog
> > HDL feature error: parameter value assignment in module instatiation is
> > not supported".  It appears like this line is causing problems :
> > WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage.
> > Any ideas?  I don't really have the time to go through every module and
> > correct errors...
> > --
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> >
>
>
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