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Re: [pci] run simulation problems

To: pci@opencores.org
Subject: Re: [pci] run simulation problems
From: ikhelifi@vt.edu
Date: Wed, 24 Jul 2002 19:37:46 -0100
Reply-To: pci@opencores.org
Sender: owner-pci@opencores.org
Hi
  I just tried running the run_pci_sim_regr.scr, but all it prints out
is:
Variable syntax
I also looked at the design document, and it doesn't talk about how to
run the simulation. Is there anywhere in the docs where it explains
how to run an actual simulation? I am familiar with PCI and such, but
not with verilog or ncsim. Is there another version I should've
downloaded? I downloaded everything yesterday.
Thanks for your help
ines


----- Original Message ----- 
From: "Miha Dolenc" <mihad@o... > 

To: <pci@o... > 
Date: Wed, 24 Jul 2002 18:59:04 +0200 
Subject: Re: [pci] run simulation problems 

> 
> 
> Hello guys! 
> 
> I'm sorry about that! 
> 
> The script run_pci_sim.scr is out of date. 
> Also the README.txt file is out of date, saying that you run the 
> simulation 
> with this script. 
> 
> The script you must run is run_pci_sim_regr.scr 
> 
> I think the usage is described in a design document. 
> If not or you still have problems, send another email. 
> 
> I'll get rid of this files ASAP. 
> 
> Regards, 
> Miha Dolenc 
> 
> ----- Original Message ----- 
> From: "Ines Khelifi" <ikhelifi@v... > 
> To: <pci@o... > 
> Sent: Wednesday, July 24, 2002 5:58 PM 
> Subject: [pci] run simulation problems 
> 
> 
> > Hi all 
> > 
> >  I just suscribed to this listserv, so I am not sure about all 
> the 
> previous 
> > messages that we sent out about my problem. 
> > I downloaded the PCI core testbench, and tried to run a 
> simulation with : 
> > run_pci_sim.scr, but this is what I get: 
> > ncvlog: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design 
> Systems, Inc. 
> > file: ../../../rtl/verilog/pci_parity_check.v 
> >         module worklib.PCI_PARITY_CHECK:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_target_unit.v 
> >         module worklib.PCI_TARGET_UNIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wb_addr_mux.v 
> >         module worklib.WB_ADDR_MUX:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/cbe_en_crit.v 
> >         module worklib.CBE_EN_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/fifo_control.v 
> >         module worklib.FIFO_CONTROL:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/out_reg.v 
> >         module worklib.OUT_REG:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_tpram.v 
> >         module worklib.PCI_TPRAM:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wb_master.v 
> >         module worklib.WB_MASTER:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/conf_cyc_addr_dec.v 
> >         module worklib.CONF_CYC_ADDR_DEC:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/frame_crit.v 
> >         module worklib.FRAME_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_target32_clk_en.v 
> >         module worklib.PCI_TARGET32_CLK_EN:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pciw_fifo_control.v 
> >         module worklib.PCIW_FIFO_CONTROL:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wb_slave.v 
> >         module worklib.WB_SLAVE:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/conf_space.v 
> >         module worklib.CONF_SPACE:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/frame_en_crit.v 
> >         module worklib.FRAME_EN_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/par_crit.v 
> >         module worklib.PAR_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pciw_pcir_fifos.v 
> >         module worklib.PCIW_PCIR_FIFOS:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wb_slave_unit.v 
> >         module worklib.WB_SLAVE_UNIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/frame_load_crit.v 
> >         module worklib.FRAME_LOAD_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_bridge32.v 
> >         module worklib.PCI_BRIDGE32:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_target32_devs_crit.v 
> >         module worklib.PCI_TARGET32_DEVS_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/perr_crit.v 
> >         module worklib.PERR_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wbr_fifo_control.v 
> >         module worklib.WBR_FIFO_CONTROL:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/cur_out_reg.v 
> >         module worklib.CUR_OUT_REG:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_decoder.v 
> >         module worklib.PCI_DECODER:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_target32_interface.v 
> >         module worklib.PCI_TARGET32_INTERFACE:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/perr_en_crit.v 
> >         module worklib.PERR_EN_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wbw_fifo_control.v 
> >         module worklib.WBW_FIFO_CONTROL:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/decoder.v 
> >         module worklib.DECODER:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_in_reg.v 
> >         module worklib.PCI_IN_REG:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/serr_crit.v 
> >         module worklib.SERR_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wbw_wbr_fifos.v 
> >         module worklib.WBW_WBR_FIFOS:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/delayed_sync.v 
> >         module worklib.DELAYED_SYNC:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/irdy_out_crit.v 
> >         module worklib.IRDY_OUT_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_io_mux.v 
> >         module worklib.PCI_IO_MUX:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_io_mux_ad_en_crit.v 
> >         module worklib.PCI_IO_MUX_AD_EN_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_io_mux_ad_load_crit.v 
> >         module worklib.PCI_IO_MUX_AD_LOAD_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_target32_sm.v 
> >         module worklib.PCI_TARGET32_SM:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/serr_en_crit.v 
> >         module worklib.SERR_EN_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/delayed_write_reg.v 
> >         module worklib.DELAYED_WRITE_REG:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/mas_ad_en_crit.v 
> >         module worklib.MAS_AD_EN_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/mas_ad_load_crit.v 
> >         module worklib.MAS_AD_LOAD_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_master32_sm.v 
> >         module worklib.PCI_MASTER32_SM:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_target32_stop_crit.v 
> >         module worklib.PCI_TARGET32_STOP_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/synchronizer_flop.v 
> >         module worklib.synchronizer_flop:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/async_reset_flop.v 
> >         module worklib.async_reset_flop:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/mas_ch_state_crit.v 
> >         module worklib.MAS_CH_STATE_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_master32_sm_if.v 
> >         module worklib.PCI_MASTER32_SM_IF:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_target32_trdy_crit.v 
> >         module worklib.PCI_TARGET32_TRDY_CRIT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/top.v 
> >         module worklib.TOP:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/pci_rst_int.v 
> >         module worklib.PCI_RST_INT:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/sync_module.v 
> >         module worklib.SYNC_MODULE:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../rtl/verilog/wb_tpram.v 
> >         module worklib.WB_TPRAM:v 
> >                 errors: 0, warnings: 0 
> > ncvlog: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design 
> Systems, Inc. 
> > file: ../../../bench/verilog/wb_master32.v 
> >         module worklib.WB_MASTER32:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/wb_master_behavioral.v 
> >         module worklib.WB_MASTER_BEHAVIORAL:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/system.v 
> >         module worklib.SYSTEM:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/pci_blue_arbiter.v 
> >         module worklib.pci_blue_arbiter:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/pci_bus_monitor.v 
> >         module worklib.pci_bus_monitor:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/pci_behaviorial_device.v 
> >         module worklib.pci_behaviorial_device:v 
> >                 errors: 0, warnings: 0 
> >         module worklib.delayed_test_pad:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/pci_behaviorial_master.v 
> >         module worklib.pci_behaviorial_master:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/pci_behaviorial_target.v 
> >         module worklib.pci_behaviorial_target:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/wb_slave_behavioral.v 
> >         module worklib.WB_SLAVE_BEHAVIORAL:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/wb_bus_mon.v 
> >         module worklib.WB_BUS_MON:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/pci_behavioral_iack_target.v 
> >         module worklib.PCI_BEHAVIORAL_IACK_TARGET:v 
> >                 errors: 0, warnings: 0 
> > file: ../../../bench/verilog/pci_unsupported_commands_master.v 
> >         module worklib.pci_unsupported_commands_master:v 
> >                 errors: 0, warnings: 0 
> > run_pci_sim.scr: [[: not found 
> > run_pci_sim.scr: [[: not found 
> > run_pci_sim.scr: [[: not found 
> > ncsim: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design 
> Systems, Inc. 
> > ncsim: *F,NOSNAP: snapshot 'worklib.bridge32:fun' does not 
> exist in the 
> > libraries. 
> > 
> > I don't know anything about Verilog and ncsim, so I am not 
> sure what that 
> > means. Any help would be appreciated. 
> > Thank you 
> > ines 
> > 
> > 
> 
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