Re: [pci] PCIU configuration read

["Miha Dolenc" <mihad@opencores.org>]

If you access configuration space with memory read command, it will be
present wherever you put its base address(BAR0).
But if you are talking about, that if you set base address to 0x0 and it
responds to 0x10000000, then this is certainly wrong. Let me know!

Regards,
Miha Dolenc

----- Original Message -----
From: "henryjeng" <henryjeng@mail.acard.com>
To: <pci@opencores.org>
Sent: Monday, July 01, 2002 11:57 PM
Subject: [pci] PCIU configuration read


>
> Dear Sir:
>    I am now trying your PCI bridge which is post on the www.opencores.com
.
>    I use the IP in HOST mode and implement the read-only configuration
image
> by comment out the define  NO_CNF_IMAGE.
>    And in the "PCI IP Core Design document" page 32,  "Configuration
Reads"
> section describe that "It can be performed
>    with MEM READ or CONF READ commands.
>    I try to read the content of configuration space via the "PCI target
> unit" of the IP CORE.
>    First, I use the PCI device model on the testbench you provided to
> generate CONF READ, and it works all right.
>    Then I use the PCI device model on the testbench you provided to
generate
> MEM READ and set the address as 0x00000000, and it work all right.
>    I can read the Device ID and Vendor ID of the configuration space ( the
> value is 0x00012321 , right?)!
>    What confused me is that when I use the PCI device model on the
testbench
> you provided to generate MEM READ and set the address as 0x10000000,
>    and the PCI target unit still return the content of  configuration
space
> ( correct Device ID and Vendor ID ).
>    Same condition will happen on MEM READ address equal to 0x00000004 and
> 0x10000004, 0x00000008 and 0x10000008 .......and so on.
>     Is this your intent design? Or do I miss something? I think the
> configuration space should only be placed on 0x00000000 !
>     Thanks for your patient to help.
>
>     Henry Jeng
>
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