[pci] Clock Domain Issues

[Dave Kroetsch <dkroetsch@videolocus.com>]

Has anyone been successful in running the PCI core with the PCI side 
running at one clock and the wishbone running off another?  I have tried 
running the PCI side at 33MHz and the wishbone side at various 
frequencies ranging from 6MHz to 60MHz, and I'm running into problems.  

I'm only testing the PCI target right now (as a guest in a PC system), 
and I'm using the OpenCore DMA  register file as a target.  (I have also 
tried my own register as a target) I've brought some of the wishbone 
signals (including cyc, ack, we, stb...) out so I can scope them.  The 
tests I have tried include:
	1) Writing single words
	2) reading single words
	3) writing bursts of 2 words
	4) writing bursts in the pattern 1-2-1

I'm having problems with the PCI bridge generating improper wishbone 
accesses and even hanging the PC!  This is being implemented on a 
Xilinx Virtex2 FPGA in a PC running linux.

Some of the symptoms include:
	1) The OpenCore PCI Bridge will generate extra wishbone
                 transactions.  eg. a PCI write of 4 words will sometimes 
                 work properly and sometimes generate 5 or 6 word writes
                 on the wishbone bus.
	
	2) The bridge will enter a state where NO transactions from
                 the PCI side will even make it across to the wishbone bus,
                 and the transactions eventually time out

	3) The bridge will hang, such that wishbone transactions are
                 CONSTANTLY being initiated and no finishing (despite the
                 fact that they are being ACKed repeatedly)

            4) The bridge enters a state where it ends EVERY attempted
                  transaction with a PCI STOPn and never asserts TRDYn.  
                  This never allows the transaction to succeed.  The PC
                  continuously retries until a watchdog kicks, and it reboots.

If I run the wishbone side at the PCI_CLK, this all seems to go away.  It 
would seem there is a problem with the clock domain crossing.  Can 
anyone provide any insight?

Thanks,
	Dave Kroetsch
             dkroetsch@videolocus.com
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