[pci] pci core status

["MikeJ" <mikej@freeuk.com>]

Just a quick update chaps.

I've got hold of the 2.2 PCI spec now, and have found that the simulation
models I got from Opencores (ms32pci etc) don't allow me to test the core
sufficiently- especially with regards to fast back to back transfers and
output enable timing.
I've almost finished writing my own, and I would like to upload the
simulation suite (vhdl) shortly so somebody else can check for any errors !
How would I go about doing this ?
Could we set up a new directory for the vhdl core and test set?

Cheers,
MikeJ

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