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[pci] RE: [oc] Interested
Hi guys
the last few days were really heavy-loaded...sorry for the delay.
At the moment there are several issues for me:
First: I came accross the pci_blue_interface and since there are some
similarities between the pci core development and this project I was
wondering if someone already figured out if we can share some efforts
(test framework or even design concepts)?
Second: Tools. Free Verilog tools are a rare thing out there (or did I
missed anything?).
Cheers
Oliver
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