[pci] PCI

[Damjan Lampret <damjanlampret@yahoo.com>]

Hi Ovidiu,

I know you are busy preparing for Canada. In case you'll have some time
I would like to ask you if you can prepare some PCI timing diagrams for
me. I am currently working on Verilog synthesizable RTL of PCI master
and target controllers. I think I'll need some test benches soon and I
wonder if I could use your PCIsim. Problem is that it is in VHDL and
here I only have Verilog. So if you could do some timing digrams with
your PCIsim and I would then use these timing digrams for reference.
One possibility would also be if you save timing information as test
vectors. Any other idea? Do you have some detailed PCI timing diagrams
(I already have PCI 2.2 standard).

regards,
Damjan

PS This PCI interface will be one of the interfaces of OR1K.




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