RE: [fpu] fmul synthesis

["Rudolf Usselmann" <russelmann@hotmail.com>]

Damjan,

did you turn re-timing on in DC ?

This should safe a lot of cycle time, specially in fmul, as there
are two registers back to back in the input stage.
Re-timing will move registers around and optimize the cycle time. It
would be equivalent to breaking up the multiplier itself and inserting
a pipeline stage - except it is done automatically ...

Best Regards,
rudi


>From: owner-fpu@opencores.org [mailto:owner-fpu@opencores.org]On Behalf
>Of Damjan Lampret
>
>
>I also synthesized fmul (version in the CVS). Clock cycle of 8.95ns.
>Same libs and operating conditions (2.5v, 25c). If operating conditions
>are changed to 2.75v and temp 0c then you get about 10% better
>performance. Power requirements (according to DC) are roughly about
>283mW (I forgot to mention power requirments for fasu which are about
>123mW). Numbers for power are probably very rough since DC doesn't have
>a clue what typical input vectors are.
>
>--damjan
>

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