RE: [fpu] multiplier

["Rudolf Usselmann" <rudi@inet.co.th>]

Jamil,

I have a single precision multiply core 90% complete. It is very similar
to my Add/Sub core. It does all the normalizations and adjustments, etc.

I did not write the actual multiply function. Synopsys Design Compiler does
a pretty good job with these primitives (just like the adder in the FASU),
that I don't want to spend the time to reinvent the wheel. If you think you
can write a multiplier that will be faster then what Design Compiler will
generate, then go for it !!!  (I wouldn't hold my breath thou ... ;*)

If you want to write a divide block, let me know and I won't bother with
that and let you write it. If you want to write it, we need to synch on the
requirements and specifications.

rudi


> From: owner-fpu@opencores.org [mailto:owner-fpu@opencores.org]On Behalf
> Of Jamil Khatib
> Subject: [fpu] multiplier
> 
> 
> Hi,
> I'd like to start working on the multiplier
> 
> The main idea is to use a Booth multiplier and wallace
> tree, Do you have suggestions. 
> there are some implementations that can be fast on
> FPGAs check
> http://users.ids.net/~randraka/multipli.htm
> 
> Regards
> Jamil Khatib