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Re: [fpu] Add/Sub Unit Test Vectors
> > I think it should be.
>
> You can not answer a OR question with a "yes" ! ;*)
>
> Which one do you think it should be ?
> a) part of the fpu project
> b) separate core
Sorry for teh confusion, yes it should be part of the
FPU.
> > Do you think that c program is suitable for
> generating
> > test vecotrs? I am not sure if the core is written
> > inverilog. I know in that I VHDL you have to write
> a
> > test bench and supply the test vectors and since
> these
> > vectors have different operations and large values
> we
> > should build a simple method "may be generic for
> all
> > projects" that can be used in the verifications
> either
> > in C or perl or any other language.
>
> 1) The core is written in Verilog
>
> 2) The goal was to have a C program that generates
> simple test
> vectors that should be useful for floating point
> cores. I am
> not familiar with VHDL, but in Verilog you can fill
> a memory
> structure from an external file. The idea was for
> the C program
> to spit out the following output:
>
> operation | operand | operand | expected |
> expected
> type 3:0 | a 31:0 | b 31:0 | result 31:0 |
> exceptions
> | | | |
> INF,NAN,DIV0
>
>
> Each line would have the above format, the operands
> and the
> expected result would be in IEEE single precision
> format.
> The test bench can read in a file with the above
> information
> and apply/verify the device under test.
>
I was not thinking of your code in this way but it
seems the same as my idea except how do you enter the
values to the C code.
> There will be as many lines as the user requested
> from the C
> program. Each line is one test vector.
>
Are The test going to begenerated automatically
"randomly" or user will enter each value?
> > This method should take some simple and human
> readable
> > commands and numbers then generate the vecorts
> based
> > on it.
>
> The C program will take a number of commands and
> generate test
> vectors base on those commands.
what Do you think about the parsing of the commands in
C? what types of commands you want? (operation &
values )
>
> > "I tried to make small vhdl functions that
> converts
> > from readable numbers to IEEE std floating bits
> but I
> > do not know if it has any use"
>
> I think this is not necessary. If an error is
> detected, then I
> have to "decode" and understand the floating point
> numbers and
> their format no matter if they are presented in the
> "readable"
> format or not ...
but the errors are excpected to be much less and you
do not need always to check the bits (32 or may be
later 80)
>
> > Further we can compare results from both the c
> > language that runs on IEEE CPU and the simulation
> > output.
>
> Exactly ! That's why we wanted to have a C program
> that generates
> the test vectors.
>
> >
> > I do not agree with you on that at least for teh
> first
> > step, I prefere to make it generic more toward
> FPGA
> > then after veryfing its functionality we can start
> the
> > next optimization phase.
>
> The code that I'm writing (see fasu.v in CVS) is
> very general code.
So lets stay generic and high performance side, agree?
> Even though Damjan is targeting standard cell for
> the first implementation,
> you can take the code and run it through FPGA
> Compiler and target your
> favorite FPGA. There is nothing that will prevent
> you from implementing
> the core in an FPGA.
>
All cores
> will have a 4 stage pipeline, and will be able to
> perform an floating
> point operation every cycle. this might not be the
> best choice for an
> FPGA implementation, if you are area limited and not
> to concerned about
But I think you can get some good performance with
piplined architecutres on FPGAs
> performance. Perhaps, later, I will design
> additional cores, that are
> very small but slow ...
OK agree.
>
>
project
> > definition according to the project template I
> sent
> > few weeks ago but I did not get any comment.
> >
> > there are many people ask for a start point for
> new
> > projects but they do not have any guidness so we
> > should agree on some project template and give it
> high
> > priority
>
> I think you should be careful with project templates
> etc. This entire
> site and it's projects are based on people devoting
> their free time to
> contribute IP cores. You should let everybody work
> in a way s/he is most
> productive. Project templates are for large
> companies and manages who don't
> know what they are doing - I've been in to many big
> name companies with
> clueless managers. If you don't like the style of
> any submitted core, you
> can repackage and resubmit it again !
This template is only a guid line not a must
One thing we should consider in all cores that we have
to support larger internal sizes (more than 23) or to
support double pressison internally to allow
compatiblility with the IEEE std calculations and
results. "I'll give more information about this point
later"
Regards
Jamil Khatib
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