Re: [openrisc] memory question

["Damjan Lampret" <lampret@opencores.org>]

I don't know if you mean the same flash prefix logic as I am, but there was
a simple logic fix to start execution from flash from address 0x100 and then
move sram to 0x0 and flash above.

regards,
Damjan

----- Original Message -----
From: <mrmclean@cablespeed.com>
To: <openrisc@opencores.org>
Sent: Tuesday, April 22, 2003 4:33 PM
Subject: [openrisc] memory question


> All,
> I'm converting the SOC demo that ran on the XVS-800 to a FPGA board
> that has only SRAM (similar to the Avnet board). I looked through the
> verilog at the top level and noticed it was changing the flash prefix for
> decoding flash accesses. I am still not sure of the big picture here, is
> the xess demo running from flash and the sram is used for data?
>
> Thanks
>    Mark
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